pipeif.v

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
/* All rights are reserved. Reproduction in whole or in part is                 */
/* prohibited without the written consent of the copyright owner.               */
/* SJTU reserves the right to make changes without notice at                    */
/* any time. The software is provided as is and SJTU makes                      */
/* no warranty, expressed, implied or statutory, including but not limited to   */
/* any implied warranty of merchantability or fitness for any particular        */
/* purpose, or that the use will not infringe any third party patent, copyright */
/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module pipeif(clk,rst,ien,status,pc,iclk,iaddr,idata,irw,nextpc,npreg,ir);
    input clk;
    input rst;
    input ien;
    output[1:0] status;
    reg [1:0] status;
    reg [1:0] istatus;
    input[31:0] pc;
    reg iclken;
    output iclk;
    output [31:0] iaddr;
    input [31:0] idata;
    output irw;
    output [31:0] nextpc;
    
    output [31:0] ir;
    reg [31:0] ir;
    wire [31:0] wir;
    output [31:0] npreg;
    reg[31:0] npreg;
    wire [31:0] wnpreg;
//////////////////////////////////////////////////    
    reg [31:0] ipc;
/////////////////////////////////////////////////
    and ick(iclk,iclken,clk);
    assign irw =1;
    assign iaddr = ipc;
    assign nextpc =pc+4;  
    always @(posedge clk or negedge rst)
    begin
       if (~rst)
          begin
             iclken <=0;
             status<=0;
             istatus<=0;
          end
        else
           begin
            if(ien)
				begin
					ipc <= pc;
					iclken <=1;
					npreg <= nextpc;
					istatus <= 2'b01;
				end
			else
			    begin
					istatus <= 2'b00;
			    end
            end
    end
    
    always @(negedge clk)
    begin
       ir = idata; 
       iclken =0;
       status = istatus;
    end
    
endmodule