pipeex.v

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
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/* prohibited without the written consent of the copyright owner.               */
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/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module pipeex(clk,rst,ien,status,
op,opt,rs1,rs2,rs2op,rs2sf,rda,rdata,
rsf,rs1r,rs2r,rs2sfr,rdatar,sbit , 
opout,aluout,rdaout,rdataout);
   input clk;
   input rst;
   input ien;
   output[1:0] status;
   reg[1:0] status;
   input[7:0] op;
   input[3:0] opt;
   input[31:0] rs1;
   input[31:0] rs2;
   input[3:0] rs2op;
   input[31:0] rs2sf;
   input[4:0] rda;
   input[31:0] rdata;
   input[3:0] rsf;
   input[`RENAMEREGWIDTH-1:0] rs1r;
   input[`RENAMEREGWIDTH-1:0] rs2r;
   input[`RENAMEREGWIDTH-1:0] rs2sfr;
   input[`RENAMEREGWIDTH-1:0] rdatar;
   input sbit;
   output[1:0] opout;
   reg [1:0] opout;
   output[31:0] aluout;
   reg [31:0] aluout;
   output[4:0] rdaout;
   reg[4:0] rdaout;
   output[31:0] rdataout;
   reg[31:0] rdataout;
   
   reg[1:0] iopout;
   reg[32:0] ialuout;
   reg[4:0] irdaout;
   
   
   reg[1:0]  istatus;
   reg[7:0]  iop;
   reg[3:0]  iopt;
   reg[31:0] irs1;
   reg[31:0] irs2;
   reg[31:0] irs2o;
   reg[3:0]  irs2op;
   reg[31:0] irs2sf;
   reg[4:0] irda;
   reg[31:0] irdata;
   reg[3:0] irsf;
   reg[`RENAMEREGWIDTH-1:0] irs1r;
   reg[`RENAMEREGWIDTH-1:0] irs2r;
   reg[`RENAMEREGWIDTH-1:0] irs2sfr;
   reg[`RENAMEREGWIDTH-1:0] irdatar;
   reg isbit;
   wire[3:0]  ivalid;
   wire[3:0]  valid;
   integer i;
   
   wire nflags = ialuout[31];
   wire zflags = ~(| ialuout[31:0]);
   wire cflags = ialuout[32];
   wire vflags = irs1[31]^irs2o[31]^ialuout[31]^ialuout[32];
   
   assign ivalid[0] = armrf.valid[irs1r];
   assign ivalid[1] = armrf.valid[irs2r];
   assign ivalid[2] = armrf.valid[irs2sfr];
   assign ivalid[3] = armrf.valid[irdatar];
   
   assign valid[0] = armrf.valid[rs1r];
   assign valid[1] = armrf.valid[rs2r];
   assign valid[2] = armrf.valid[rs2sfr];
   assign valid[3] = armrf.valid[rdatar];
  
   
always @(posedge clk or negedge rst)
begin
   if (~rst)
   begin
		  status <=0; 
		  istatus<=0;
   end
  else
   begin
		   if ((status ==2'b00)||(status ==2'b01))
		   begin
				if (ien)
					begin
						 iop <=op;
						 iopt<=opt;
						 irs2op<=rs2op;
						 irda <= rda;
						 isbit<=sbit;
						
						  if (!(({armrf.busy[rdatar],armrf.busy[rs2sfr],armrf.busy[rs2r],armrf.busy[rs1r]}& rsf) == rsf))
							 $display("ERROR!");
						   if (!((valid & rsf) == rsf))
							begin
								istatus <= 2'b10;
								irs1r<= rs1r;
								 irs2r <= rs2r;
								 irs2sfr <=rs2sfr;
								 ialuout <=0;
								 irsf <=rsf;
								 irdatar<= rdatar;
								 irdata<= rdata;
								 irs1<=rs1;
								 irs2<=rs2;
								 irs2sf <= rs2sf;
							end
							else
							begin
								 istatus <= 2'b01;
							if (rsf[0])
							begin
								if (armrf.req[rs1r])
								armrf.req[rs1r] <= armrf.req[rs1r] -1;
								irs1 <= armrf.data[rs1r];
							end
							else
							  irs1 <= rs1;
							   
							if (rsf[1])
							begin
							#1
							if (armrf.req[rs2r])
								armrf.req[rs2r] <= armrf.req[rs2r] -1;
								irs2 <= armrf.data[rs2r];
							end
							else
							   irs2<= rs2;
							if (rsf[2])
							begin
							#1
							if (armrf.req[rs2sfr])
								armrf.req[rs2sfr] <= armrf.req[rs2sfr] -1;
								irs2sf <= armrf.data[rs2sfr];
							end
							else
							  irs2sf<= rs2sf;
							
							if (rsf[3])
							begin
							#1
							if (armrf.req[rdatar])
								armrf.req[rdatar] <= armrf.req[rdatar] -1;
								irdata <= armrf.data[rdatar];
							end
							else
							   irdata <= irdata;
							
							irsf <=0;
							end
					end
				else
					begin
					 ;
					end
		   end
		   else // else status
		   begin
		   
				if (!(({armrf.busy[irdatar],armrf.busy[irs2sfr],armrf.busy[irs2r],armrf.busy[irs1r]}& rsf) == rsf))
					  $display("ERROR!");		
						
					if (!((ivalid & rsf) == rsf))
							 istatus <= 2'b10;
						else
						begin
							istatus <= 2'b01;
							if (irsf[0])
							begin
								if (armrf.req[irs1r])
								armrf.req[irs1r] <= armrf.req[irs1r] -1;
								irs1 <= armrf.data[irs1r];
							end
							if (irsf[1])
							begin
							#1
							if (armrf.req[irs2r])
								armrf.req[irs2r] <= armrf.req[irs2r] -1;
								irs2 <= armrf.data[irs2r];
							end
							if (irsf[2])
							begin
							#1
							if (armrf.req[irs2sfr])
								armrf.req[irs2sfr] <= armrf.req[irs2sfr] -1;
								irs2sf <= armrf.data[irs2sfr];
							end
							
							if (irsf[3])
							begin
							#1
							if (armrf.req[irdatar])
								armrf.req[irdatar] <= armrf.req[irdatar] -1;
								irdata <= armrf.data[irdatar];
							end
							irsf <=0;
						end
		   
		   
		   end
	
   end
end

always @(posedge clk)
begin
#5
 if ((istatus == 2'b01) && (isbit))
	begin
		   armrf.cpsr[31:28] <={nflags,zflags,cflags,vflags};
		   armrf.cpsrws<=0;
	end
  if ((istatus == 2'b01) && (isbit))
  begin
  
   if (iop == `MSR)
	begin
		iopout =`MAOPNOP;
		if (irs1 & 4'b1000)
		 armrf.cpsr[31:28] <= irs2[31:28];
    end
  
  end
end
always @(iop or iopt or irs1 or irs2 or irs2op or irsf or
irs2sf or istatus or ivalid)
begin
	
	if (istatus == 2'b01)
	begin
	///////////////////////////////////////////////////////////////////////////////
	  
	 case(irs2op)
		 `SFROR:
		   begin
		   ///////////////////////////////////////
//		   for(i=31;i>=0;i=i-1)
		   begin   
//			irs2[i] = irs2[(31+i-irs2sf) %32];
		   end
		   
		   /////////////////////////////////////////
		   end
		 `SFLSL:
		   begin
			irs2 = irs2<< irs2sf;
		   end
		 `SFLSR:
		   begin
			irs2 = irs2>> irs2sf;
		   end
		 `SFASR:
		   begin
		   irs2 = irs2>> irs2sf;
		   end
		 `SFMUL:
		   begin
		   irs2 = irs2 * irs2sf;
		   end
		 default:
		   begin
		   
		   end
		 
	  endcase
	//////////////////////////////////////////////////////////////////////////////
			
			case(iop)
			   `NOP:
				begin
					istatus = 0;
				end
			   `LD:
				begin
				  iopout =`MAOPLD;
				  ialuout = irs1+irs2;
				end 
			   `ST:
				begin
				  iopout =`MAOPST;
				  ialuout = irs1+irs2;
				  
				end 
			   `MOV:
				begin
				 iopout =`MAOPWB;
				 ialuout = {1'b0,irs1+irs2};
				 irs2o = irs2;
				end
			   `ORR:
				begin
				 iopout =`MAOPWB;
				 ialuout = {1'b0,irs1|irs2};
				  irs2o = irs2;
				end
			   `AND:
				begin
				 iopout =`MAOPWB;
				 ialuout = {1'b0,irs1&irs2};
				  irs2o = irs2;
				end
			   `ADD:
				begin
				iopout =`MAOPWB;
				ialuout = irs1+irs2;
				 irs2o = irs2;
				end
			   `ADC:
				begin
				iopout =`MAOPWB;
					ialuout = irs1+irs2 + armrf.cpsr[29];
				end
			   `SUB:
				begin
				 iopout =`MAOPWB;
				  ialuout = irs1+(~irs2)+1;
				  irs2o = ~irs2;
				end
			   `MVN:
				begin
				 iopout =`MAOPWB;
				   ialuout = ~irs2;
					irs2o = ~irs2;
				end
			   `CMP:
				begin
				 iopout =`MAOPNOP;
				   ialuout = irs1+(~irs2)+1;
					irs2o = ~irs2;
				end
			   `CMN:
				begin
				 iopout =`MAOPNOP;
				   ialuout = irs1+irs2;
					irs2o = irs2;
				end
			   `MLA:
				begin
				   iopout =`MAOPWB;
				   ialuout = irs1+irs2;
					irs2o = irs2;
				end
			   `MUL:
				begin
				 iopout =`MAOPWB;
				 ialuout = irs2;
				 irs2o = irs2;
				end
				`MRS:
				begin
				 iopout =`MAOPWB;
				 ialuout = armrf.cpsr;
				 irs2o =0;
				end
				`MSR:
				begin
				 iopout =`MAOPNOP;
				 if (irs1 & 4'b1000)
				 begin
					irs2o =0;
				 end
				 
				end
				default:
				  istatus =0;
			   endcase
			   
			  
			   

		   end
end




always @(posedge clk or negedge rst)
begin
   if (~rst)
   begin
		  status <=0; 
		  istatus<=0;
   end
  else
   begin
   #5
		   if (istatus ==2'b01)
		   begin
				if (ien)
					begin
					   if ((iop!= `LD) && ( iop !=`ST)&& ( iop !=`NOP))
					   begin
						//////////////////////////////////////////////////////////
								if (armrf.writealloc[irda])
								 begin
									armrf.data[armrf.reqNaddr[irda]] <= ialuout;
									armrf.valid[armrf.reqNaddr[irda]] <=1;
								 end
					  /////////////////////////////////////////////////////////
						end	
						else
						begin
						
						end
					end
				else
					begin
					 ;
					end
		   end
		   else // else status
		   begin
		  
		   end
   end
end


always @(negedge clk)
begin
  status<= istatus;
  opout<= iopout;
  aluout<=ialuout;
  rdaout<= irda;
  rdataout<= irdata;
end



always @(negedge clk)
begin
	
end


endmodule