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📄 regfile.v

📁 别处下载的sarm9
💻 V
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/********************************************************************************//* Copyright @ 2006 by SOME of SJTU                                             *//* All rights are reserved. Reproduction in whole or in part is                 *//* prohibited without the written consent of the copyright owner.               *//* SJTU reserves the right to make changes without notice at                    *//* any time. The software is provided as is and SJTU makes                      *//* no warranty, expressed, implied or statutory, including but not limited to   *//* any implied warranty of merchantability or fitness for any particular        *//* purpose, or that the use will not infringe any third party patent, copyright *//* or trademark. SJTU should not be liable for any loss or damage arising from  *//* its use. you can redistribute it and/or                                      *//*  modify it under the terms of the GNU Lesser General Public                  *//*  License as published by the Free Software Foundation; either                *//*  version 2 of the License, or (at your option) any later version.            *//********************************************************************************//** *        PROJECT: Simple ARM Core *      COPYRIGHT: SOME of SJTU 2006 *       $RCSfile: ,v $ *      $Revision:  $ *         AUTHOR: Thomas.Luo *         E_MAIL: microbear@sjtu.edu.cn *       LANGUAGE: V *    DESCRIPTION:  * *      DOCUMENTS:  **/`include "sarm9h.v"module regfile(rst);   input rst;   integer i;   reg[31:0] cpsr;   reg[2:0]  cpsrws;      // cpsr write;   reg[31:0] regs[0:15];   ///////////////////////////////////////////////   // rename REG   reg [4:0] regrename[0:`MAXRENAMEREGS-1];   reg[31:0] data[0:`MAXRENAMEREGS-1];   reg       valid[0:`MAXRENAMEREGS-1];   reg       busy[0:`MAXRENAMEREGS-1];   reg[2:0]  req[0:`MAXRENAMEREGS-1];   ////////////////////////////////////////////////   //write status   reg[15:0] writealloc;   reg[`RENAMEREGWIDTH-1:0]  reqNaddr[0:15];   ///////////////////////////////////////////////   always @(negedge rst)   begin      cpsr<=0;      cpsrws<=0;      for(i=0;i<16;i=i+1)             regs[i]<=0;      for(i=0;i<`MAXRENAMEREGS;i=i+1)      begin             regrename[i]<=0;             data[i]<=0;             valid[i]<=0;             busy[i]<=0;             req[i]<=0;      end                   writealloc <=0;         for(i=0;i<16;i=i+1)         reqNaddr[i]<=4'b1111;       endendmodule

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