compact_flash_ide_hard_disk_interface.map.rpt

这是一个基于FPGA的CF卡读写程序

; Maximum Number of M4K Memory Blocks                                ; -1           ; -1                                    ;
; Maximum Number of M-RAM Memory Blocks                              ; -1           ; -1                                    ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off                                   ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On                                    ;
+--------------------------------------------------------------------+--------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Thu Aug 23 21:53:05 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Compact_Flash_IDE_hard_disk_interface -c Compact_Flash_IDE_hard_disk_interface
Error: VHDL Use Clause error at atacntl.vhd(4): design library "work" does not contain primary unit "common"
Error: Ignored construct ata at atacntl.vhd(7) because of previous errors
Error: Ignored construct pioIntfc at atacntl.vhd(101) because of previous errors
Error: VHDL error at atacntl.vhd(133): entity "pioIntfc" is used but not declared
Error: VHDL error at atacntl.vhd(135): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(136): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(137): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(138): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(141): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(142): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(143): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(144): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(145): object "natural" is used but not declared
Error: VHDL error at atacntl.vhd(148): object "unsigned" is used but not declared
Error: VHDL error at atacntl.vhd(151): object "unsigned" is used but not declared
Error: VHDL error at atacntl.vhd(152): object "unsigned" is used but not declared
Error: VHDL error at atacntl.vhd(153): object "unsigned" is used but not declared
Error: VHDL error at atacntl.vhd(154): object "unsigned" is used but not declared
Error: VHDL error at atacntl.vhd(167): object "std_logic" is used but not declared
Info: Found 0 design units, including 0 entities, in source file atacntl.vhd
Error: VHDL Use Clause error at atatst300.vhd(4): design library "work" does not contain primary unit "common"
Error: VHDL Use Clause error at atatst300.vhd(5): design library "work" does not contain primary unit "mem"
Error: VHDL Use Clause error at atatst300.vhd(6): design library "work" does not contain primary unit "ata"
Error: Ignored construct ataTst300 at atatst300.vhd(11) because of previous errors
Error: VHDL error at atatst300.vhd(32): entity "ataTst300" is used but not declared
Error: VHDL error at atatst300.vhd(33): object "natural" is used but not declared
Error: VHDL error at atatst300.vhd(34): object "std_logic" is used but not declared
Error: VHDL error at atatst300.vhd(35): object "unsigned" is used but not declared
Error: VHDL error at atatst300.vhd(36): object "std_logic" is used but not declared
Error: VHDL error at atatst300.vhd(37): object "std_logic" is used but not declared
Error: VHDL error at atatst300.vhd(38): object "std_logic" is used but not declared
Error: VHDL error at atatst300.vhd(39): object "unsigned" is used but not declared
Error: VHDL error at atatst300.vhd(40): object "unsigned" is used but not declared
Error: VHDL error at atatst300.vhd(41): object "unsigned" is used but not declared
Error: VHDL error at atatst300.vhd(42): object "std_logic" is used but not declared
Error: VHDL error at atatst300.vhd(43): object "unsigned" is used but not declared
Error: VHDL error at atatst300.vhd(44): object "std_logic" is used but not declared
Error: VHDL error at atatst300.vhd(45): object "std_logic_vector" is used but not declared
Error: VHDL error at atatst300.vhd(46): object "std_logic" is used but not declared
Info: Found 0 design units, including 0 entities, in source file atatst300.vhd
Info: Found 2 design units, including 0 entities, in source file common.vhd
    Info: Found design unit 1: common
    Info: Found design unit 2: common-body
Error: VHDL Use Clause error at memtest.vhd(5): design library "work" does not contain primary unit "rand"
Error: Ignored construct mem at memtest.vhd(8) because of previous errors
Error: VHDL Use Clause error at memtest.vhd(41): design library "work" does not contain primary unit "rand"
Error: Ignored construct memTest at memtest.vhd(43) because of previous errors
Error: VHDL error at memtest.vhd(67): entity "memTest" is used but not declared
Error: VHDL error at memtest.vhd(79): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(80): object "std_logic" is used but not declared
Error: VHDL error at memtest.vhd(81): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(82): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(83): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(86): object "std_logic" is used but not declared
Error: VHDL error at memtest.vhd(87): object "std_logic" is used but not declared
Error: VHDL error at memtest.vhd(88): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(89): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(90): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(91): object "integer" is used but not declared
Error: VHDL error at memtest.vhd(92): object "unsigned" is used but not declared
Error: VHDL error at memtest.vhd(96): object "seed" is used but not declared
Error: VHDL error at memtest.vhd(100): object "randGen" is used but not declared
Info: Found 0 design units, including 0 entities, in source file memtest.vhd
Info: Found 3 design units, including 1 entities, in source file randgen.vhd
    Info: Found design unit 1: rand
    Info: Found design unit 2: randGen-arch
    Info: Found entity 1: randGen
Error: Quartus II Analysis & Synthesis was unsuccessful. 57 errors, 0 warnings
    Error: Processing ended: Thu Aug 23 21:53:08 2007
    Error: Elapsed time: 00:00:04