randgen.vhd

这是一个基于FPGA的CF卡读写程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


package rand is

component randGen	-- loadable LFSR random number generator
	generic
	(
		DATA_WIDTH: natural := 8
	);
	port
	(
		clk:	in std_logic;		-- main clock input
		cke:	in std_logic;		-- clock enable
		ld:		in std_logic;		-- load enable for seed
		seed:	in unsigned(DATA_WIDTH-1 downto 0);		-- random number seed value
		rand:	out unsigned(DATA_WIDTH-1 downto 0)		-- output for random number
	);
end component;

end package rand;


-- loadable LFSR random number generator
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity randGen is
	generic
	(
		DATA_WIDTH: natural := 8
	);
	port
	(
		clk:	in std_logic;		-- main clock input
		cke:	in std_logic;		-- clock enable
		ld:		in std_logic;		-- load enable for seed
		seed:	in unsigned(DATA_WIDTH-1 downto 0);		-- random number seed value
		rand:	out unsigned(DATA_WIDTH-1 downto 0)		-- output for random number
	);
end randGen;

architecture arch of randGen is
	signal r : unsigned (rand'length-1 downto 0);	-- random number shift register
	signal new_bit : std_logic;		-- feedback bit into LSb of LFSR
begin
	-- use the length parameter to select the bits in the shift register
	-- which will be XOR'ed to compute the bit fed back into the 
	-- least significant bit of the shift register
	new_bit <=
				r(1)  xor r(0)                      when r'length=2 else
				r(2)  xor r(1)                      when r'length=3 else
				r(3)  xor r(2)                      when r'length=4 else
				r(4)  xor r(2)                      when r'length=5 else
				r(5)  xor r(4)                      when r'length=6 else
				r(6)  xor r(3)                      when r'length=7 else
				r(7)  xor r(5)  xor r(4)  xor r(3)  when r'length=8 else
				r(11) xor r(10) xor r(7)  xor r(5)  when r'length=12 else
				r(15) xor r(12) xor r(11) xor r(10) when r'length=16 else
				r(19) xor r(16)                     when r'length=20 else
				r(23) xor r(22) xor r(21) xor r(16) when r'length=24 else
				r(27) xor r(24)                     when r'length=28 else
				r(31) xor r(30) xor r(29) xor r(9)  when r'length=32 else
				r(r'length-1);

	update_shift_register:
	process(clk)
	begin
		if clk'EVENT and clk='1' then	-- update register on rising clock edge
			if cke = '0' then	-- reload current value if clock disabled
				r <= r;
			elsif ld='1' then	-- load with seed value
--				r <= seed;
				r <= (others=>'1');
			else						-- otherwise, shift register left and append feedback bit
				r <= r(r'length-2 downto 0) & new_bit;
			end if;
		end if;
	end process;

	rand <= r;	-- output the random number in the shift register

end arch;