compact_flash_ide_hard_disk_interface.map.qmsg

这是一个基于FPGA的CF卡读写程序

{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned atatst300.vhd(39) " "Error: VHDL error at atatst300.vhd(39): object \"unsigned\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 39 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned atatst300.vhd(40) " "Error: VHDL error at atatst300.vhd(40): object \"unsigned\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 40 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned atatst300.vhd(41) " "Error: VHDL error at atatst300.vhd(41): object \"unsigned\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 41 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic atatst300.vhd(42) " "Error: VHDL error at atatst300.vhd(42): object \"std_logic\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 42 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned atatst300.vhd(43) " "Error: VHDL error at atatst300.vhd(43): object \"unsigned\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 43 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic atatst300.vhd(44) " "Error: VHDL error at atatst300.vhd(44): object \"std_logic\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 44 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic_vector atatst300.vhd(45) " "Error: VHDL error at atatst300.vhd(45): object \"std_logic_vector\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 45 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic atatst300.vhd(46) " "Error: VHDL error at atatst300.vhd(46): object \"std_logic\" is used but not declared" {  } { { "atatst300.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/atatst300.vhd" 46 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "atatst300.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file atatst300.vhd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "common.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file common.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 common " "Info: Found design unit 1: common" {  } { { "common.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/common.vhd" 5 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 common-body " "Info: Found design unit 2: common-body" {  } { { "common.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/common.vhd" 25 -1 0 } }  } 0}  } {  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "rand work memtest.vhd(5) " "Error: VHDL Use Clause error at memtest.vhd(5): design library \"work\" does not contain primary unit \"rand\"" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 5 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "mem memtest.vhd(8) " "Error: Ignored construct mem at memtest.vhd(8) because of previous errors" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 8 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "rand work memtest.vhd(41) " "Error: VHDL Use Clause error at memtest.vhd(41): design library \"work\" does not contain primary unit \"rand\"" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 41 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "memTest memtest.vhd(43) " "Error: Ignored construct memTest at memtest.vhd(43) because of previous errors" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 43 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNCOMPILED_ENTITY" "memTest memtest.vhd(67) " "Error: VHDL error at memtest.vhd(67): entity \"memTest\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 67 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(79) " "Error: VHDL error at memtest.vhd(79): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 79 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic memtest.vhd(80) " "Error: VHDL error at memtest.vhd(80): object \"std_logic\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 80 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(81) " "Error: VHDL error at memtest.vhd(81): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 81 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(82) " "Error: VHDL error at memtest.vhd(82): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 82 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(83) " "Error: VHDL error at memtest.vhd(83): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 83 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic memtest.vhd(86) " "Error: VHDL error at memtest.vhd(86): object \"std_logic\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 86 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic memtest.vhd(87) " "Error: VHDL error at memtest.vhd(87): object \"std_logic\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 87 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(88) " "Error: VHDL error at memtest.vhd(88): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 88 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(89) " "Error: VHDL error at memtest.vhd(89): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 89 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(90) " "Error: VHDL error at memtest.vhd(90): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 90 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "integer memtest.vhd(91) " "Error: VHDL error at memtest.vhd(91): object \"integer\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 91 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "unsigned memtest.vhd(92) " "Error: VHDL error at memtest.vhd(92): object \"unsigned\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 92 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "seed memtest.vhd(96) " "Error: VHDL error at memtest.vhd(96): object \"seed\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 96 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "randGen memtest.vhd(100) " "Error: VHDL error at memtest.vhd(100): object \"randGen\" is used but not declared" {  } { { "memtest.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/memtest.vhd" 100 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "memtest.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file memtest.vhd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "randgen.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file randgen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rand " "Info: Found design unit 1: rand" {  } { { "randgen.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/randgen.vhd" 6 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 randGen-arch " "Info: Found design unit 2: randGen-arch" {  } { { "randgen.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/randgen.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 randGen " "Info: Found entity 1: randGen" {  } { { "randgen.vhd" "" { Text "D:/Compact_Flash_IDE_hard_disk_interface/randgen.vhd" 31 -1 0 } }  } 0}  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 57 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 57 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Thu Aug 23 21:53:08 2007 " "Error: Processing ended: Thu Aug 23 21:53:08 2007" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:04 " "Error: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}