atatst300.vhd

这是一个基于FPGA的CF卡读写程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.mem.all;
use WORK.ata.all;


-- disk tester

entity ataTst300 is
	generic(
		BEG_ADDR: 		natural := 16#00000#;					-- beginning address
		END_ADDR: 		natural := 16#1FFFF#;					-- ending address
		BEG_TEST: 		natural := 16#00000#;					-- beginning test range address
		END_TEST: 		natural := 16#0FFFF#					-- ending test range address
	);
	port(
		fpga_init_n:	out	std_logic;								-- CPLD interface chip-select
		clk:					in	std_logic;								-- main clock input from external clock source
		dior_n:				out	std_logic;								-- disk read enable
		diow_n:				out	std_logic;								-- disk write enable
		nv_cs0_n:			out	std_logic;								-- disk command register block select
		nv_cs1_n:			out	std_logic;								-- disk control register block select
		da:						out	unsigned(2 downto 0);			-- disk register address bus
		dd:						inout unsigned(15 downto 0);	-- disk data bus
		nv_intrq:			in	std_logic;								-- disk interrupt request
		nv_dmack_n:		out	std_logic									-- disk DMA acknowledgement
	);
end ataTst300;

architecture arch of ataTst300 is
	constant ADDR_WIDTH: natural := log2(END_ADDR-BEG_ADDR+1);
	signal rst:				std_logic;												-- reset signal
	signal rstCnt:		unsigned(1 downto 0);							-- reset timer
	signal rd:				std_logic;												-- host-side read control signal
	signal wr:				std_logic;												-- host-side write control signal
	signal abort:			std_logic;												-- abort current disk command
	signal hAddr:			unsigned(ADDR_WIDTH-1 downto 0);	-- host address bus
	signal hDIn:			unsigned(15 downto 0);						-- host-side data to disk
	signal hDOut:			unsigned(15 downto 0);						-- host-side data from disk
	signal done:			std_logic;												-- disk operation complete indicator
	signal dData:			unsigned(15 downto 0);						-- local disk data bus
	signal outEnable:	std_logic;												-- enable local disk data bus to disk data bus
	signal progress:	std_logic_vector(1 downto 0);			-- test progress indicator
	signal err:				std_logic;												-- test error flag
	signal errbits:		unsigned(dd'range);								-- shows data bits with errors
	signal cylinder:	unsigned(15 downto 0);						-- current disk cylinder
begin

	fpga_init_n <= '1';	-- disable CPLD interface

	-- assert the reset for a few clock cycles after startup
	process(clk)
	begin
		if(clk'event and clk='1') then
			if rstCnt /= TO_UNSIGNED(1,rstCnt'length) then
				rst <= '1';
				rstCnt <= rstCnt + 1;
			else
				rst <= '0';					-- remove reset
			end if;
		end if;
	end process;

	-- generic memory tester module
	u0: memTest
	generic map(
		DATA_WIDTH => hDIn'length,
		ADDR_WIDTH => hAddr'length,
		BEG_TEST => BEG_TEST,
		END_TEST => END_TEST,
		STEP_SIZE => 1
	)
	port map(
		clk => clk,							-- master clock
		rst => rst,							-- reset
		done => done,						-- disk operation complete
		dIn => hDOut,						-- host-side data from disk goes to memory tester
		rd => rd,								-- host-side disk read control from memory tester
		wr => wr,								-- host-side disk write control from memory tester
		abort => abort,					-- memory tester requests abort of the current disk command
		addr => hAddr,					-- host-side address from memory tester
		dOut => hDIn,						-- host-side data to disk comes from memory tester
		progress => progress,		-- current phase of memory test
		errbits => errbits,			-- shows data bits with errors
		err => err							-- memory test error flag
	);

	-- Ignore the lower 8-bits of the host address from the memory tester
	-- because the 256 words in a sector are addressed sequentially.
	-- But use the next nine address bits to select the cylinder where
	-- the sector is located.
	cylinder(8 downto 0) <= hAddr(16 downto 8);
	cylinder(15 downto 9) <= (others=>'0'); 	-- zero the upper bits of the cylinder address

	-- disk interface
	u1: ataCntl
	generic map(
		FREQ => 50_000					-- operating frequency in KHz
	)
	port map(
		-- host side
		clk => clk,							-- master clock
		rst => rst,							-- reset
		rd => rd,								-- initiate read operation
		wr => wr,								-- initiate write operation
		abort => abort,					-- abort the current read/write operation
		done => done,						-- read or write operation is done
		head => x"0",						-- fix the disk head for data access
		cylinder => cylinder,		-- cylinder for data access from memory tester
		sector => x"05",				-- fix the sector for data access
		hDIn => hDIn,						-- data from host	to disk
		hDOut => hDOut,					-- data from disk to host
		status => open,					-- diagnostic status for the operation		

		-- disk side
		dior_n => dior_n,				-- disk register read-enable
		diow_n => diow_n,				-- disk register write-enable
		cs0_n => nv_cs0_n,			-- disk command block register select
		cs1_n => nv_cs1_n,			-- disk control block register select
		da => da(2 downto 0),		-- register address
		ddOut => dData,					-- data to disk
		ddOutEnbl => outEnable,	-- enable data outputs to disk
		ddIn => dd,							-- data from disk
		intrq => nv_intrq,			-- interrupt request from disk
		dmack_n => nv_dmack_n		-- DMA cknowledge
	);

	-- indicate the phase of the memory test on the LED	
	dd <= 
				-- tristate the disk databus when data is read from the disk during memory test	read phase
				"ZZZZZZZZZZZZZZZZ" when progress /= "11" and outEnable='0' else
				-- drive the disk databus with data from the memory tester during memory test write phase
				dData when progress /= "11" and outEnable='1' else
				-- display an "E" after the memory test completes if an error was detected
				errbits(15 downto 8) & "01111001" when progress="11" and err=YES else
				-- display an "O" after the memory test completes if no error was found
				"0000000000111111";

end arch;