init.c

移植UCOS于增强型５１单片机上

#include "init.h"
#include "msp430x14x.h"
void WatchDogStop(void)
{
  WDTCTL = WDTPW+((WDTCTL&0xff)|WDTHOLD); // Stop watchdog timer  
}

//
void InitClock(long mclkdiv,long smclkdiv)
{
	unsigned int i;
	//turnoff lfxt1
	//DCOCTL  &=~XTS;
	__bis_SR_register(__get_SR_register() | OSCOFF);
	//OSCOFF=1;
	
	//turn on XT2
	BCSCTL1 	&=~XT2OFF;
	
	//waitting for XT2 stable
	while((IFG1&OFIFG))//if the OFIFG bit is 1
	{
		IFG1	&=~OFIFG;		//clear the oscillator fault flag
		for(i=0;i<100;i++)		//because cpu will auto set the OFIFG flag bit while
			;					//the oscillator fault
								//delay some clock cycle
	}
	
	for(i=0;i<10000;i++)		//delay for XT2 become stable
		;
		
	//select MClk's divider
	switch(mclkdiv)
	{
		case div1:			//分频系数1
			BCSCTL2	&=~DIVM0;
			BCSCTL2	&=~DIVM1;		//分频系数为2
			break;
		case div2:			//2
			BCSCTL2	|=DIVM0;
			BCSCTL2	&=~DIVM1;		
			break;
		case div4:			//4
			BCSCTL2	&=~DIVM0;
			BCSCTL2	|=DIVM1;		
			break;
		case div8:			//8
			BCSCTL2	|=DIVM0;
			BCSCTL2	|=DIVM1;		
			break;
	}
	
	
	//select SMclk's divider
	switch(smclkdiv)
	{
		case div1:			//分频系数1
			BCSCTL2	&=~DIVS0;
			BCSCTL2	&=~DIVS1;		
			break;
		case div2:			//2
			BCSCTL2	|=DIVS0;
			BCSCTL2	&=~DIVS1;		
			break;
		case div4:			//4
			BCSCTL2	&=~DIVS0;
			BCSCTL2	|=DIVS1;		
			break;
		case div8:			//8
			BCSCTL2	|=DIVS0;
			BCSCTL2	|=DIVS1;		
			break;
	}
	
	
	//IFG1	&=~OFIFG;		//clear the oscillator fault flag
	
	BCSCTL2	|=SELS;			//select XT2CLK as the clock source of SMClk
	BCSCTL2	&=~SELM0;		//select XT2CLK as the clock source of MClk
	BCSCTL2	|=SELM1;
	IFG1	&=~OFIFG;		//clear the oscillator fault flag	
}

//IO口初始化,不用的IO口设置成输出
void InitIO(void)
{	
	P1DIR	=0xff;		//P1定义为输出
	P1OUT	=0xff;
	
	P2OUT 	|=0xff;	
	P2DIR	|=0xff;		//P2 defined as output port
		
	P3OUT 	|=0xff;
	P3DIR	|=0xff;		//P3 defined as a output port
		
	P4OUT	 =0xff;
	P4DIR	|=0xff;
	
	P5OUT	|=0xff;
	P5DIR	|=0xff;
	
	P5SEL	|=BIT5;
	
	P6OUT	|=0xff;
	P6DIR	|=0xff;	
}

void ClrOutWDG(void)
{
	P5OUT ^=BIT4;
}