main.c

来自「ADS下的bios工程」· C语言 代码 · 共 182 行

#include <bios/s3c2410x.h>
#include <bios/stdio.h>
#include <bios/flash_amd.h>

extern int Write_Device(unsigned char *, int);
void nand_flash(void);

char dbgin(void)
{
	while( !(CSR_READ(UTRSTAT0) & 0x1) ) ;
	return (unsigned char)(CSR_READ(URXH0));
}

void dbgc( char ch )
{
	while( !(CSR_READ(UTRSTAT0) & 0x4) ) ;
	CSR_WRITE(UTXH0, ch);
	if(ch == '\n') {
		while( !(CSR_READ(UTRSTAT0) & 0x4) ) ;
		CSR_WRITE(UTXH0, '\r');
	}
}

void dbgs( unsigned char *ptr )
{
	while( *ptr )
		dbgc( *ptr++ );
}

void dbgout(char *fmt, ...)
{
	va_list ap;
	char buf[256];

	va_start(ap, fmt);
	vsprintf(buf, fmt, ap);
	dbgs(buf);
	va_end(ap);
}

extern void call_swi(int, int, int);
extern void InvalidateTLB(unsigned long);
#define v_to_p(v_addr)  ((unsigned long)((*(unsigned long *)(0xC0004000+(v_addr>>18))) & 0xFFFFF000) + (v_addr & 0xFFFFF))
extern int _edata, _entry;

void start_update(int size, unsigned char *start)
{
	volatile unsigned long real_size, val;
	unsigned char *src;
	unsigned int chip=0, i;

	dbgout("\nCheck JP2 Setting : +-+ +\n");
	dbgout("waiting for key input....\n");
	dbgin();
	dbgout("\nROM Write Start...\n");
	src = (unsigned char *)&_edata;
	val = &_edata - &_entry;
	real_size = size - val;
	switch(flash_get_manuf_code(0)) {
		case AMDPART:
			switch(flash_get_device_id(0)) {
				case ID_AM29DL800T:
					chip = AM29DL800T; break;
				case ID_AM29DL800B:
					chip = AM29DL800B; break;
				case ID_AM29LV800T:
					chip = AM29LV800T; break;
				case ID_AM29LV800B:
					chip = AM29LV800B; break;
				case ID_AM29LV160B:
					chip = AM29LV160B; break;
				case ID_AM29LV400B:
					chip = AM29LV400B; break;
				default: break;
			}
		default:
			break ;
	}
	init_flash(chip);
	for(i=0; i<4; i++) flash_sector_erase_int(i);
	flash_write_string(0, 0, src, real_size);

	dbgout("\nROM Write Complete...\n");
	dbgout("Now rebooting...");
	CSR_WRITE(WTDAT, 0x8000);
	CSR_WRITE(WTCNT, 0x8000);
	CSR_WRITE(WTCON, 0x8021);
	while(1) {
		dbgout("."); 
		{ int i; for(i=0; i<0xfffff; i++); }
	}
}

unsigned char Buf[512], Spare[16];

void nand_flash(void) {
	unsigned char m_id, d_id;
	int i;

	for(i=0; i<512; i++) Buf[i] = i;
	for(i=0; i<16; i++) Spare[i] = 0xFF;

	CSR_WRITE(NFCONF, ((0x1<<15)|(0x1<<14)|(0x0<<13)|(0x1<<12)|(0x1<<11)|(0x0<<8)|(0x2<<4)|(0x0<<0)));

	/* NAND Flash reset */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) & ~(1<<11));
	CSR_WRITE(NFCMD, 0xff);		/* reset command : 0xFF */
	{int i; for(i=0; i<0x10; i++); }	/* Twb(max) : 100ns */
	while( !(CSR_READ(NFSTAT)&0x1) );
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<11));

	/* NAND Flash ID read */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) & ~(1<<11));
	CSR_WRITE(NFCMD, 0x90);		/* ID read command : 0x90 */
	CSR_WRITE(NFADDR, 0x00);	/* address : 0x00 */
	{int i; for(i=0; i<0x10; i++); }	/* Twb(max) : 100ns */
	{int i; for(i=0; i<0x6; i++); }		/* Treadid(max) : 35ns */
	m_id = CSRB_READ(NFDATA);
	d_id = CSRB_READ(NFDATA);
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<11));
	dbgout("Maker ID : %x, Device ID : %x\n", m_id, d_id);

	/* Block Erase : 0x0 */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) & ~(1<<11));
	CSR_WRITE(NFCMD, 0x60);		/* Block Erase Setup command : 0x60 */
	CSR_WRITE(NFADDR, 0x00);	/* Block Address(A9~A16) : 0x00 */
	CSR_WRITE(NFADDR, 0x00);	/* Block Address(A17~A22) : 0x00 */
	{int i; for(i=0; i<0x8; i++); }	/* Twc(min) : 50ns */
	CSR_WRITE(NFCMD, 0xD0);		/* Block Erase command : 0xD0 */
	{int i; for(i=0; i<0x10; i++); }	/* Twb(max) : 100ns */
	while( !(CSR_READ(NFSTAT)&0x1) );
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<11));

	/* Write Page : 0x0 */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<12));	/* Initialize ECC */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) & ~(1<<11));
	CSR_WRITE(NFCMD, 0x00);		/* Move Pointer Position command : 0x00 */
	CSR_WRITE(NFCMD, 0x80);		/* Page Data Input command : 0x80 */
	CSR_WRITE(NFADDR, 0x00);	/* Column Address(A0~A7) : 0x00 */
	CSR_WRITE(NFADDR, 0x00);	/* First Page Address(A9~A16) : 0x00 */
	CSR_WRITE(NFADDR, 0x00);	/* Second Page Address(A17~A22) : 0x00 */
	{int i; for(i=0; i<0x10; i++); }	/* Twb(max) : 100ns */
	for(i=0; i<512; i++) {
		CSRB_WRITE(NFDATA, Buf[i]);
	}
	Spare[0] = CSRB_READ(NFECC0);
	Spare[1] = CSRB_READ(NFECC1);
	Spare[2] = CSRB_READ(NFECC2);
	for(i=0; i<16; i++) CSRB_WRITE(NFDATA, Spare[i]);
	CSR_WRITE(NFCMD, 0x10);		/* Page Program command : 0x10 */
	{int i; for(i=0; i<0x10; i++); }	/* Twb(max) : 100ns */
	while( !(CSR_READ(NFSTAT)&0x1) );	/* Tr(max) : 7us */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<11));

	/* Read Page : 0x0 */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<12));	/* Initialize ECC */
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) & ~(1<<11));
	CSR_WRITE(NFCMD, 0x00);		/* Sequential Raw Read command : 0x00 */
	CSR_WRITE(NFADDR, 0x00);	/* Column Address(A0~A7) : 0x00 */
	CSR_WRITE(NFADDR, 0x00);	/* First Page Address(A9~A16) : 0x00 */
	CSR_WRITE(NFADDR, 0x00);	/* Second Page Address(A17~A22) : 0x00 */
	{int i; for(i=0; i<0x10; i++); }	/* Twb(max) : 100ns */
	while( !(CSR_READ(NFSTAT)&0x1) );	/* Tr(max) : 7us */
	for(i=0; i<512; i++) {
		Buf[i] = CSRB_READ(NFDATA);
	}
	for(i=0; i<16; i++) Spare[i] = CSRB_READ(NFDATA);
	CSR_WRITE(NFCONF, CSR_READ(NFCONF) | (1<<11));

	for(i=0; i<512; i+=16) {
		dbgout("[%02x][%02x][%02x][%02x] ", Buf[i+0], Buf[i+1], Buf[i+2], Buf[i+3]);
		dbgout("[%02x][%02x][%02x][%02x] ", Buf[i+4], Buf[i+5], Buf[i+6], Buf[i+7]);
		dbgout("[%02x][%02x][%02x][%02x] ", Buf[i+8], Buf[i+9], Buf[i+10], Buf[i+11]);
		dbgout("[%02x][%02x][%02x][%02x]\n", Buf[i+12], Buf[i+13], Buf[i+14], Buf[i+15]);
	}
	dbgout("\n");
	for(i=0; i<16; i++) {
		dbgout("[%02x]", Spare[i]);
	}
	dbgout("\n");
}