crt0.s
来自「ADS下的bios工程」· S 代码 · 共 509 行
S
509 行
#include <bios/s3c2410x.h>#include <bios/linkage.h> .text .macro delay ldr r0, =0xffff1: subs r0, r0, #1 bne 1b .endm@ Entry .globl _entry_entry:/*------------------------------------------------------ * Setup interrupt vector table ------------------------------------------------------*/ b reset_handler b undef_handler b swi_handler b prefetch_handler b abort_handler nop b irq_handler b fiq_handler@ Setup vectored interrupt nop@ldr pc,=HandlerEINT0 @ 0x20 nop@ldr pc,=HandlerEINT1 @ 0x24 nop@ldr pc,=HandlerEINT2 @ 0x28 nop@ldr pc,=HandlerEINT3 @ 0x2c nop@ldr pc,=HandlerEINT4 @ 0x30 nop@ldr pc,=HandlerRTICK @ 0x34 nop @ 0x38 nop @ 0x3c nop@ldr pc,=HandlerZDMA0 @ 0x40 nop@ldr pc,=HandlerZDMA1 @ 0x44 nop@ldr pc,=HandlerBDMA0 @ 0x48 nop@ldr pc,=HandlerBDMA1 @ 0x4c nop@ldr pc,=HandlerWDT @ 0x50 nop@ldr pc,=HandlerUERROR @ 0x54 nop @ 0x58 nop @ 0x5c nop@ldr pc,=HandlerTIMER0 @ 0x60 nop@ldr pc,=HandlerTIMER1 @ 0x64 nop@ldr pc,=HandlerTIMER2 @ 0x68 nop@ldr pc,=HandlerTIMER3 @ 0x6c nop@ldr pc,=HandlerTIMER4 @ 0x70 nop@ldr pc,=HandlerTIMER5 @ 0x74 nop @ 0x78 nop @ 0x7c nop@ldr pc,=HandlerURXD0 @ 0x80 nop@ldr pc,=HandlerURXD1 @ 0x84 nop@ldr pc,=HandlerIIC @ 0x88 nop@ldr pc,=HandlerSIO @ 0x8c nop@ldr pc,=HandlerUTXD0 @ 0x90 nop@ldr pc,=HandlerUTXD1 @ 0x94 nop @ 0x98 nop @ 0x9c nop@ldr pc,=HandlerRTC @ 0xa0 nop @ 0xa4 nop @ 0xa8 nop @ 0xac nop @ 0xb0 nop @ 0xb4 nop @ 0xb8 nop @ 0xbc nop@ldr pc,=HandlerADC @ 0xc0reset_handler :/*------------------------------------------------------ * Watch-Dog Timer Disable ------------------------------------------------------*/ ldr r0,=WTCON ldr r1,=rWTCON /* watch dog disable */ str r1,[r0]/*------------------------------------------------------ * Interrupt Disable All ------------------------------------------------------*/ ldr r0,=INTMSK ldr r1,=INT_MASK_DIS /* all interrupt disable */ str r1,[r0] ldr r0,=INTSUBMSK str r1,[r0]/*------------------------------------------------------ * LOCK Time Count Setup ------------------------------------------------------*/ ldr r0,=LOCKTIME ldr r1,=rLOCKTIME str r1,[r0]/*------------------------------------------------------ * PLL & CLOCK Setup ------------------------------------------------------*/ ldr r0,=MPLLCON ldr r1,=rMPLLCON str r1,[r0] ldr r0,=UPLLCON ldr r1,=rUPLLCON str r1,[r0] ldr r0,=CLKDIVN ldr r1,=rCLKDIVN str r1,[r0]/*------------------------------------------------------ * General I/O ports Setup ------------------------------------------------------*/ ldr r0, =GPACON ldr r1, =0x7FFFFF str r1, [r0] ldr r0, =GPBCON ldr r1, =0x044555 str r1, [r0] ldr r0, =GPBUP ldr r1, =0x7FF /* All pull-up is disabled. */ str r1, [r0] ldr r0, =GPCCON ldr r1, =0xAAAA56AA str r1, [r0] ldr r0, =GPCUP ldr r1, =0xFFFF /* All pull-up is disabled. */ str r1, [r0] ldr r0, =GPDCON ldr r1, =0xAAAAAAAA str r1, [r0] ldr r0, =GPDUP ldr r1, =0xFFFF /* All pull-up is disabled. */ str r1, [r0] ldr r0, =GPECON ldr r1, =0xAAAAAAAA str r1, [r0] ldr r0, =GPEUP ldr r1, =0xFFFF str r1, [r0] ldr r0, =GPFCON ldr r1, =0xAAAA str r1, [r0] ldr r0, =GPFUP ldr r1, =0xFF str r1, [r0] ldr r0, =GPGCON ldr r1, =0xFFDDFFF9 str r1, [r0] ldr r0, =GPGUP ldr r1, =0xFFFF str r1, [r0] ldr r0, =GPHCON ldr r1, =0x2AFAAA str r1, [r0] ldr r0, =GPHUP ldr r1, =0x7FF str r1, [r0]/* * External Interrupt Control Register */ ldr r0, =EXTINT0 ldr r1, =0x22222222 /* All Falling edge triggered mode */ str r1, [r0] ldr r0, =EXTINT1 str r1, [r0] ldr r0, =EXTINT2 str r1, [r0]/*------------------------------------------------------ * Initialize debug port ------------------------------------------------------*/ bl dbg_init mov r0,#'\n' bl printch mov r0,#'l' bl printch/*------------------------------------------------------- * disable the interrupts in CPU and switch to SVC32 mode -------------------------------------------------------*/ mrs r0, cpsr bic r0, r0, #MODE_MASK orr r0, r0, #SUP_MODE | IBit | FBit msr cpsr, r0 mov r0,#'i' bl printch/*------------------------------------------------------ * Setup DRAM ------------------------------------------------------*//* ROM and DRAM Configuration(Multiple Load and Store) */ @Set memory control registers adr r0, .L_DRAM_SysInitData_Reset ldr r1, =SYS_INIT_BASE add r2, r0, #52 @End address of SMRDATA0: ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne 0b mov r0,#'a' bl printch mov r0,#'o' bl printch/*------------------------------------------------------ * Initialize MMU ------------------------------------------------------*/ ldr r1, =MMUTT_STARTADDRESS mov r0, #0x4000 mov r2, #0x01: subs r0, r0, #4 str r2, [r1], #4 /* MMU Table Clear */ bne 1b bl SYMBOL_NAME(MMU_Init)/*------------------------------------------------------ * Clear bss section and setup stack pointer ------------------------------------------------------*/.L_clear_bss_section : mov r0, #0 ldr r1, =SYMBOL_NAME(_bss_start) ldr r2, =SYMBOL_NAME(_bss_end)1: str r0, [r1], #4 cmp r1, r2 blt 1b ldr sp, =0x30280000 @hardcode, modified later/*------------------------------------------------------ * Initialize vector, in this boot code, only timer interrupt is used * setup stack pointer to end of DRAM */ bl vec_init/*------------------------------------------------------ * got a RAM size ------------------------------------------------------*/ ldr r0, =SYMBOL_NAME(ram_size) str r12, [r0]/*------------------------------------------------------ * branch to start_main() function * here is a really start point of boot code ------------------------------------------------------*/ ldr r0, =SYMBOL_NAME(_end) mrc p15, 0, r0, c1, c0, 0 bl SYMBOL_NAME(start_main) b . .ltorg/*------------------------------------------------------ * void ser_write(const char *buffer, int nr) ------------------------------------------------------*/ENTRY(ser_write) stmfd sp!, {r9 - r11, lr} bl ser_prints ldmfd sp!, {r9 - r11, pc}ENTRY(ser_stat) mov pc, lr/*------------------------------------------------------ * Define some useful macro for UART debug interface ------------------------------------------------------*/ .macro addruart,rx ldr \rx, =DEBUG_TX_BUFF_BASE .endm .macro senduart,rd,rx strb \rd, [\rx] .endm .macro busyuart,rd,rx1001: ldr \rx, =DEBUG_CHK_STAT_BASE ldr \rd, [\rx] and \rd, \rd, #DEBUG_TX_DONE_CHECK_BIT teq \rd, #DEBUG_TX_DONE_CHECK_BIT bne 1001b .endm .macro waituart,rd,rx .endm/*------------------------------------------------------ * UART printout function for debug ------------------------------------------------------*/ENTRY(dbg_init) ldr r0, =DEBUG_UARTMCON_BASE ldr r1, =DEBUG_UMCON_REG_VAL /* 0x00 */ str r1, [r0] ldr r0, =DEBUG_UARTFCON_BASE ldr r1, =DEBUG_UFCON_REG_VAL /* 0x00 */ str r1, [r0] ldr r0, =DEBUG_UARTLCON_BASE ldr r1, =DEBUG_ULCON_REG_VAL /* 0x03 */ str r1, [r0] ldr r0, =DEBUG_UARTCONT_BASE ldr r1, =DEBUG_UCONT_REG_VAL /* 0x245 */ str r1, [r0] ldr r0, =DEBUG_UARTBAUD_BASE ldr r1, =DEBUG_UBAUD_REG_VAL str r1, [r0] mov pc, lrENTRY(printreg) mov r13, lr mov r5, #28 mov r6, r0 mov r7, #0xf1001: and r0, r7, r6, lsr r5 cmp r0, #10 addge r0, r0, #'a'-10 @ greater or equal addlt r0, r0, #'0' @ less than bl printch subs r5, r5, #4 bpl 1001b mov r0, #'\n' bl printch mov r0, #'\r' bl printch mov pc, r13ENTRY(printascii) addruart r3 b 2f1: waituart r2, r3 senduart r1, r3 busyuart r2, r3 teq r1, #'\n' moveq r1, #'\r' beq 1b2: teq r0, #0 ldrneb r1, [r0], #1 teqne r1, #0 bne 1b mov pc, lrENTRY(printch) addruart r3 mov r1, r0 mov r0, #0 b 1bENTRY(FindRAMSize)@ mov r0, #0x30000000 @ start at base of physical RAM@ mov r1, #0x100 @ 4 byte grain is fine enoughchecksize: mov r7, r1 @ keep step size in r7 mov r6, r0 @ keep base address in r6 mov r5, r6 @ r5 is probe address ldr r4, [r6, #0] @ preserve original base contents mov r2, #0x55 @ build adjacent bit tests orr r2, r2, #0xAA00 @ make 0xAA55 pattern orr r2, r2, r2, lsl #16 @ final pattern 0xAA55AA55 mvn r3, r2 @ use inverse copy as alternate pattern @ Move up memory insteps, probing each location with two different @ patterns to see if memory is present, and checking the base of @ memory too (to detect aliasing of wrapped memory). @ save AA55AA55 in base which should be there until wrapped str r2, [r6, #0] @ store first pattern at base ldr r0, [r6, #0] @ and read back cmp r0, r2 @ check okay bne checksizefail @ give up if not @ byte testing valuable as ARM broadcasts 4 bytes @ and any faulty write enables will corrupt other bytescheckbyte0: @ check byte writes work independently (endian-independent) ldrb r1, [r6, #0] @ byte at a time mov r0, #0xA5 @ using local pattern strb r0, [r6, #0] @ test byte 0 ldrb r0, [r6, #0] @ read back cmp r0, #0xA5 @ test bne checksizefail @ fail if different strb r1, [r6, #0] @ restore byte ldr r0, [r6, #0] @ test word still intact cmp r0, r2 @ still pattern one bne checksizefail @ fail if differentcheckbyte1: @ in line for zero stack usage, etc. ldrb r1, [r6, #1] @ preserve byte 1 mov r0, #0xA5 @ using local pattern strb r0, [r6, #1] @ test byte 1 ldrb r0, [r6, #1] @ read back cmp r0, #0xA5 @ test bne checksizefail @ fail if different strb r1, [r6, #1] @ restore byte ldr r0, [r6, #0] @ test word still intact cmp r0, r2 @ still pattern one bne checksizefail @ fail if differentcheckbyte2: ldrb r1, [r6, #2] @ preserve byte 2 mov r0, #0xA5 @ using local pattern strb r0, [r6, #2] @ test byte 2 ldrb r0, [r6, #2] @ read back cmp r0, #0xA5 @ test bne checksizefail @ fail if different strb r1, [r6, #2] @ restore byte ldr r0, [r6, #0] @ test word still intact cmp r0, r2 @ still pattern one bne checksizefail @ fail if differentcheckbyte3: ldrb r1, [r6, #3] @ preserve byte 3 mov r0, #0xA5 @ using local pattern strb r0, [r6, #3] @ test byte 3 ldrb r0, [r6, #3] @ read back cmp r0, #0xA5 @ test bne checksizefail @ fail if different strb r1, [r6, #3] @ restore byte ldr r0, [r6, #0] @ test word still intact cmp r0, r2 @ still pattern one bne checksizefail @ fail if different add r5, r6, r7 @ r5 is probe address (base+step)checksizeloop: ldr r1, [r5, #0] @ preserve probed value in r1 ldr r8, [r5, r7] str r2, [r5, #0] @ store first pattern str r3, [r5, r7] @ inverse pattern ldr r0, [r5, #0] @ read it back cmp r0, r2 @ is it correct? bne checksizefail @ no working memory here str r1, [r5, #0] @ restore probed value add r5, r5, r7 @ r5 is probe address (base+step) ldr r0, [r5, #0] @ read it back cmp r0, r3 @ is it correct? movne r1, r8 bne checksizefail @ not working @ if reads and writes okay did last write wrap to base? ldr r0, [r6, #0] str r8, [r5, #0] @ restore probed value cmp r0, r2 @ base still reads as first pattern? bne checksizefail addeq r5, r5, r7 @ if okay then increment probe beq checksizeloop @ and loop, else fall through to fail @ Address of first failing location in r2, original contents in r6 @ Original contents of base in r7checksizefail: str r1, [r5, #0] @ restore original contents of probe str r4, [r6, #0] @ restore original contents of base sub r0, r5, r6 @ valid size is (probe - base) mov pc, lr/*------------------------------------------------------ * Define variable ------------------------------------------------------*/ .align 4sdram_str: .asciz "SDRAM Size : 0x" .align 4.L_DRAM_SysInitData_Reset: .long rBWSCON .long rBANKCON0 .long rBANKCON1 .long rBANKCON2 .long rBANKCON3 .long rBANKCON4 .long rBANKCON5 .long rBANKCON6 .long rBANKCON7 .long rREFRESH .long rBANKSIZE .long rMRSRB6 .long rMRSRB7⌨️ 快捷键说明
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