s3c2410x.h

来自「ADS下的bios工程」· C头文件 代码 · 共 1,191 行 · 第 1/4 页

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#define	EP2_FIFO			(ASIC_BASE+0x0A0001CB)#define	EP3_FIFO			(ASIC_BASE+0x0A0001CF)#define	EP4_FIFO			(ASIC_BASE+0x0A0001D3)#define	EP1_DMA_CON			(ASIC_BASE+0x0A000203)#define	EP1_DMA_UNIT		(ASIC_BASE+0x0A000207)#define	EP1_DMA_FIFO		(ASIC_BASE+0x0A00020B)#define	EP1_DMA_TX_LO		(ASIC_BASE+0x0A00020F)#define	EP1_DMA_TX_MD		(ASIC_BASE+0x0A000213)#define	EP1_DMA_TX_HI		(ASIC_BASE+0x0A000217)#define	EP2_DMA_CON			(ASIC_BASE+0x0A00021B)#define	EP2_DMA_UNIT		(ASIC_BASE+0x0A00021F)#define	EP2_DMA_FIFO		(ASIC_BASE+0x0A000223)#define	EP2_DMA_TX_LO		(ASIC_BASE+0x0A000227)#define	EP2_DMA_TX_MD		(ASIC_BASE+0x0A00022B)#define	EP2_DMA_TX_HI		(ASIC_BASE+0x0A00022F)#define	EP3_DMA_CON			(ASIC_BASE+0x0A000243)#define	EP3_DMA_UNIT		(ASIC_BASE+0x0A000247)#define	EP3_DMA_FIFO		(ASIC_BASE+0x0A00024B)#define	EP3_DMA_TX_LO		(ASIC_BASE+0x0A00024F)#define	EP3_DMA_TX_MD		(ASIC_BASE+0x0A000253)#define	EP3_DMA_TX_HI		(ASIC_BASE+0x0A000257)#define	EP4_DMA_CON			(ASIC_BASE+0x0A00025B)#define	EP4_DMA_UNIT		(ASIC_BASE+0x0A00025F)#define	EP4_DMA_FIFO		(ASIC_BASE+0x0A000263)#define	EP4_DMA_TX_LO		(ASIC_BASE+0x0A000267)#define	EP4_DMA_TX_MD		(ASIC_BASE+0x0A00026B)#define	EP4_DMA_TX_HI		(ASIC_BASE+0x0A00026F)#else /* BIG_ENDIAN */#define	FUNC_ADDR_REG		(ASIC_BASE+0x0A000140)#define	PWR_REG				(ASIC_BASE+0x0A000144)#define	EP_INT_REG			(ASIC_BASE+0x0A000148)#define	USB_INT_REG			(ASIC_BASE+0x0A000158)#define	EP_INT_EN_REG		(ASIC_BASE+0x0A00015C)#define	USB_INT_EN_REG		(ASIC_BASE+0x0A00016C)#define	FRAME_NUM1_REG		(ASIC_BASE+0x0A000170)#define	INDEX_REG			(ASIC_BASE+0x0A000178)#define	EP0_CSR				(ASIC_BASE+0x0A000184)#define	IN_CSR1_REG			(ASIC_BASE+0x0A000184)#define	IN_CSR2_REG			(ASIC_BASE+0x0A000188)#define	MAXP_REG			(ASIC_BASE+0x0A00018C)#define	OUT_CSR1_REG		(ASIC_BASE+0x0A000190)#define	OUT_CSR2_REG		(ASIC_BASE+0x0A000194)#define	OUT_FIFO_CNT1_REG	(ASIC_BASE+0x0A000198)#define	OUT_FIFO_CNT2_REG	(ASIC_BASE+0x0A00019C)#define	EP0_FIFO			(ASIC_BASE+0x0A0001C0)#define	EP1_FIFO			(ASIC_BASE+0x0A0001C4)#define	EP2_FIFO			(ASIC_BASE+0x0A0001C8)#define	EP3_FIFO			(ASIC_BASE+0x0A0001CC)#define	EP4_FIFO			(ASIC_BASE+0x0A0001D0)#define	EP1_DMA_CON			(ASIC_BASE+0x0A000200)#define	EP1_DMA_UNIT		(ASIC_BASE+0x0A000204)#define	EP1_DMA_FIFO		(ASIC_BASE+0x0A000208)#define	EP1_DMA_TX_LO		(ASIC_BASE+0x0A00020C)#define	EP1_DMA_TX_MD		(ASIC_BASE+0x0A000210)#define	EP1_DMA_TX_HI		(ASIC_BASE+0x0A000214)#define	EP2_DMA_CON			(ASIC_BASE+0x0A000218)#define	EP2_DMA_UNIT		(ASIC_BASE+0x0A00021C)#define	EP2_DMA_FIFO		(ASIC_BASE+0x0A000220)#define	EP2_DMA_TX_LO		(ASIC_BASE+0x0A000224)#define	EP2_DMA_TX_MD		(ASIC_BASE+0x0A000228)#define	EP2_DMA_TX_HI		(ASIC_BASE+0x0A00022C)#define	EP3_DMA_CON			(ASIC_BASE+0x0A000240)#define	EP3_DMA_UNIT		(ASIC_BASE+0x0A000244)#define	EP3_DMA_FIFO		(ASIC_BASE+0x0A000248)#define	EP3_DMA_TX_LO		(ASIC_BASE+0x0A00024C)#define	EP3_DMA_TX_MD		(ASIC_BASE+0x0A000250)#define	EP3_DMA_TX_HI		(ASIC_BASE+0x0A000254)#define	EP4_DMA_CON			(ASIC_BASE+0x0A000258)#define	EP4_DMA_UNIT		(ASIC_BASE+0x0A00025C)#define	EP4_DMA_FIFO		(ASIC_BASE+0x0A000260)#define	EP4_DMA_TX_LO		(ASIC_BASE+0x0A000264)#define	EP4_DMA_TX_MD		(ASIC_BASE+0x0A000268)#define	EP4_DMA_TX_HI		(ASIC_BASE+0x0A00026C)#endif /* LITTLE_ENDIAN *//*------------------------------------------------------------------ * IIC TIMER REGISTER DEFINITION *------------------------------------------------------------------*/#define IICCON	 		(ASIC_BASE+0x0C000000)#define IICSTAT	 		(ASIC_BASE+0x0C000004)#define IICADD	 		(ASIC_BASE+0x0C000008)#define IICDS 			(ASIC_BASE+0x0C00000C)/*------------------------------------------------------------------ * IIS CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*/#ifdef BIG_ENDIAN#define IISCON_H          	(ASIC_BASE+0x0D000000)#define IISCON          	(ASIC_BASE+0x0D000002)#define IISMOD_H           	(ASIC_BASE+0x0D000004)#define IISMOD           	(ASIC_BASE+0x0D000006)#define IISPSR_H          	(ASIC_BASE+0x0D000008)#define IISPSR          	(ASIC_BASE+0x0D00000A)#define IISFIFCON_H         (ASIC_BASE+0x0D00000C)#define IISFIFCON           (ASIC_BASE+0x0D00000E)#define IISFIF           	(ASIC_BASE+0x0D000012)#else /* BIG_ENDIAN */#define IISCON          	(ASIC_BASE+0x0D000000)#define IISMOD           	(ASIC_BASE+0x0D000004)#define IISPSR          	(ASIC_BASE+0x0D000008)#define IISFIFCON           (ASIC_BASE+0x0D00000C)#define IISFIF           	(ASIC_BASE+0x0D000010)#endif /* LITTLE_ENDIAN *//*------------------------------------------------------------------ * GPIO PORT INTERFACE REGISTER DEFINITION *------------------------------------------------------------------*/#define GPACON			(ASIC_BASE+0x0E000000)#define GPADAT			(ASIC_BASE+0x0E000004)#define GPBCON			(ASIC_BASE+0x0E000010)#define GPBDAT			(ASIC_BASE+0x0E000014)#define GPBUP			(ASIC_BASE+0x0E000018)#define GPCCON			(ASIC_BASE+0x0E000020)#define GPCDAT			(ASIC_BASE+0x0E000024)#define GPCUP			(ASIC_BASE+0x0E000028)#define GPDCON			(ASIC_BASE+0x0E000030)#define GPDDAT			(ASIC_BASE+0x0E000034)#define GPDUP			(ASIC_BASE+0x0E000038)#define GPECON			(ASIC_BASE+0x0E000040)#define GPEDAT			(ASIC_BASE+0x0E000044)#define GPEUP			(ASIC_BASE+0x0E000048)#define GPFCON			(ASIC_BASE+0x0E000050)#define GPFDAT			(ASIC_BASE+0x0E000054)#define GPFUP			(ASIC_BASE+0x0E000058)#define GPGCON			(ASIC_BASE+0x0E000060)#define GPGDAT			(ASIC_BASE+0x0E000064)#define GPGUP			(ASIC_BASE+0x0E000068)#define GPHCON			(ASIC_BASE+0x0E000070)#define GPHDAT			(ASIC_BASE+0x0E000074)#define GPHUP			(ASIC_BASE+0x0E000078)#define MISCCR			(ASIC_BASE+0x0E000080)#define DCKCON			(ASIC_BASE+0x0E000084)#define EXTINT0			(ASIC_BASE+0x0E000088)#define EXTINT1			(ASIC_BASE+0x0E00008C)#define EXTINT2			(ASIC_BASE+0x0E000090)#define EINTFLT0		(ASIC_BASE+0x0E000094)#define EINTFLT1		(ASIC_BASE+0x0E000098)#define EINTFLT2		(ASIC_BASE+0x0E00009C)#define EINTFLT3		(ASIC_BASE+0x0E0000A0)#define EINTMASK		(ASIC_BASE+0x0E0000A4)#define EINTPEND		(ASIC_BASE+0x0E0000A8)#define GSTATUS0		(ASIC_BASE+0x0E0000AC)#define GSTATUS1		(ASIC_BASE+0x0E0000B0)/*------------------------------------------------------------------ * RTC(Real Time Clock) REGISTER DEFINITION *------------------------------------------------------------------*/#ifdef BIG_ENDIAN#define RTCCON	 		(ASIC_BASE+0x0F000043)#define TICNT	 		(ASIC_BASE+0x0F000047)#define RTCALM	 		(ASIC_BASE+0x0F000053)#define ALMSEC	 		(ASIC_BASE+0x0F000057)#define ALMMIN	 		(ASIC_BASE+0x0F00005B)#define ALMHOUR 		(ASIC_BASE+0x0F00005F)#define ALMDAY	 		(ASIC_BASE+0x0F000063)#define ALMMON	 		(ASIC_BASE+0x0F000067)#define ALMYEAR 		(ASIC_BASE+0x0F00006B)#define RTCRST	 		(ASIC_BASE+0x0F00006F)#define BCDSEC	 		(ASIC_BASE+0x0F000073)#define BCDMIN	 		(ASIC_BASE+0x0F000077)#define BCDHOUR 		(ASIC_BASE+0x0F00007B)#define BCDDAY	 		(ASIC_BASE+0x0F00007F)#define BCDDATE 		(ASIC_BASE+0x0F000083)#define BCDMON	 		(ASIC_BASE+0x0F000087)#define BCDYEAR 		(ASIC_BASE+0x0F00008B)#else /* BIG_ENDIAN */#define RTCCON	 		(ASIC_BASE+0x0F000040)#define TICNT	 		(ASIC_BASE+0x0F000044)#define RTCALM	 		(ASIC_BASE+0x0F000050)#define ALMSEC	 		(ASIC_BASE+0x0F000054)#define ALMMIN	 		(ASIC_BASE+0x0F000058)#define ALMHOUR 		(ASIC_BASE+0x0F00005C)#define ALMDAY	 		(ASIC_BASE+0x0F000060)#define ALMMON	 		(ASIC_BASE+0x0F000064)#define ALMYEAR 		(ASIC_BASE+0x0F000068)#define RTCRST	 		(ASIC_BASE+0x0F00006C)#define BCDSEC	 		(ASIC_BASE+0x0F000070)#define BCDMIN	 		(ASIC_BASE+0x0F000074)#define BCDHOUR 		(ASIC_BASE+0x0F000078)#define BCDDAY	 		(ASIC_BASE+0x0F00007C)#define BCDDATE 		(ASIC_BASE+0x0F000080)#define BCDMON	 		(ASIC_BASE+0x0F000084)#define BCDYEAR 		(ASIC_BASE+0x0F000088)#endif /* LITTLE_ENDIAN */#define RTC_BASE		(RTCCON)		/* using linux/arch/arm/mach-s3c24xxx/time.c */#define RTCEN			(0x1<<0)#define CLKSEL			(0x1<<1)#define CNTSEL			(0x1<<2)#define CLKRST			(0x1<<3)#define TICK_INT_EN		(0x1<<7)#define ALMEN			(0x1<<6)#define YEAREN			(0x1<<5)#define MONEN			(0x1<<4)#define DAYEN			(0x1<<3)#define HOUREN			(0x1<<2)#define MINEN			(0x1<<1)#define SECEN			(0x1<<0)/*------------------------------------------------------------------ * A/D CONVERTER REGISTER DEFINITION *------------------------------------------------------------------*/#define ADCCON    		(ASIC_BASE+0x10000000)#define ADCTSC    		(ASIC_BASE+0x10000004)#define ADCDLY    		(ASIC_BASE+0x10000008)#define ADCDAT0    		(ASIC_BASE+0x1000000C)#define ADCDAT1    		(ASIC_BASE+0x10000010)/*------------------------------------------------------------------ * SPI CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*/#define SPCON      	    	(ASIC_BASE+0x11000000)#define SPSTA      	    	(ASIC_BASE+0x11000004)#define SPPIN      	    	(ASIC_BASE+0x11000008)#define SPPRE      	    	(ASIC_BASE+0x1100000C)#define SPTDAT      	    (ASIC_BASE+0x11000010)#define SPRDAT      	    (ASIC_BASE+0x11000014)/*------------------------------------------------------------------ * SD INTERFACE CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*/#define SDICON      	    	(ASIC_BASE+0x12000000)#define SDIPRE      	    	(ASIC_BASE+0x12000004)#define SDICmdArg      	    	(ASIC_BASE+0x12000008)#define SDICmdCon      	    	(ASIC_BASE+0x1200000C)#define SDICmdSta      	    	(ASIC_BASE+0x12000010)#define SDIRSP0      	    	(ASIC_BASE+0x12000014)#define SDIRSP1      	    	(ASIC_BASE+0x12000018)#define SDIRSP2      	    	(ASIC_BASE+0x1200001C)#define SDIRSP3      	    	(ASIC_BASE+0x12000020)#define SDIDTimer      	    	(ASIC_BASE+0x12000024)#define SDIBSize      	    	(ASIC_BASE+0x12000028)#define SDIDatCon      	    	(ASIC_BASE+0x1200002C)#define SDIDatCnt      	    	(ASIC_BASE+0x12000030)#define SDIDatSta      	    	(ASIC_BASE+0x12000034)#define SDIFSTA      	    	(ASIC_BASE+0x12000038)#ifdef BIG_ENDIAN#define SDIDAT      	    	(ASIC_BASE+0x1200003F)#else /* BIG_ENDIAN */#define SDIDAT      	    	(ASIC_BASE+0x1200003C)#endif /* LITTLE_ENDIAN */#define SDIIntMsk      	    	(ASIC_BASE+0x12000040)/* Interrupt control macro functions *//* define for direct use */#define IntMode 		(VPint(INTMOD))#define IntPend 		(VPint(INTPND))#define SrcPend 		(VPint(SRCPND))#define SrcSubPend 		(VPint(SRCSUBPND))#define SrcExtPend 		(VPint(EINTPEND))#define IntMask 		(VPint(INTMSK))#define IntSubMask 		(VPint(INTSUBMSK))#define IntExtMask 		(VPint(EINTMASK))/* used in : entry-armv.s */ #define NR_IRQS		63/* Expand Interrupt Vector Number */#define INT_SUB_ADC		62	/* ADC EOC interrupt */#define INT_SUB_TC		61	/* Touch interrupt */#define INT_SUB_UERR2	60	/* UART2 Err interrupt */#define INT_SUB_UTXD2	59	/* UART2 Tx interrupt */#define INT_SUB_URXD2	58	/* UART2 Rx interrupt */#define INT_SUB_UERR1	57	/* UART1 Err interrupt */#define INT_SUB_UTXD1	56	/* UART1 Tx interrupt */#define INT_SUB_URXD1	55	/* UART1 Rx interrupt */#define INT_SUB_UERR0	54	/* UART0 Err interrupt */#define INT_SUB_UTXD0	53	/* UART0 Tx interrupt */#define INT_SUB_URXD0	52	/* UART0 Rx interrupt */#define INT_SUB_EINT23	51	/* External interrupt23 */#define INT_SUB_EINT22	50	/* External interrupt22 */#define INT_SUB_EINT21	49	/* External interrupt21 */#define INT_SUB_EINT20	48	/* External interrupt20 */#define INT_SUB_EINT19	47	/* External interrupt19 */#define INT_SUB_EINT18	46	/* External interrupt18 */#define INT_SUB_EINT17	45	/* External interrupt17 */#define INT_SUB_EINT16	44	/* External interrupt16 */#define INT_SUB_EINT15	43	/* External interrupt15 */#define INT_SUB_EINT14	42	/* External interrupt14 */#define INT_SUB_EINT13	41	/* External interrupt13 */#define INT_SUB_EINT12	40	/* External interrupt12 */#define INT_SUB_EINT11	39	/* External interrupt11 */#define INT_SUB_EINT10	38	/* External interrupt10 */#define INT_SUB_EINT9	37	/* External interrupt9 */#define INT_SUB_EINT8	36	/* External interrupt8 */#define INT_SUB_EINT7	35	/* External interrupt7 */#define INT_SUB_EINT6	34	/* External interrupt6 */#define INT_SUB_EINT5	33	/* External interrupt5 */#define INT_SUB_EINT4 	32	/* External interrupt4 *//* Interrupt Vector Number */
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