s3c2410x.h
来自「ADS下的bios工程」· C头文件 代码 · 共 1,191 行 · 第 1/4 页
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#define DISRC0 (ASIC_BASE+0x03000000)#define DISRCC0 (ASIC_BASE+0x03000004)#define DIDST0 (ASIC_BASE+0x03000008)#define DIDSTC0 (ASIC_BASE+0x0300000C)#define DCON0 (ASIC_BASE+0x03000010)#define DSTAT0 (ASIC_BASE+0x03000014)#define DCSRC0 (ASIC_BASE+0x03000018)#define DCDST0 (ASIC_BASE+0x0300001C)#define DMASKTRIG0 (ASIC_BASE+0x03000020)#define DISRC1 (ASIC_BASE+0x03000040)#define DISRCC1 (ASIC_BASE+0x03000044)#define DIDST1 (ASIC_BASE+0x03000048)#define DIDSTC1 (ASIC_BASE+0x0300004C)#define DCON1 (ASIC_BASE+0x03000050)#define DSTAT1 (ASIC_BASE+0x03000054)#define DCSRC1 (ASIC_BASE+0x03000058)#define DCDST1 (ASIC_BASE+0x0300005C)#define DMASKTRIG1 (ASIC_BASE+0x03000060)#define DISRC2 (ASIC_BASE+0x03000080)#define DISRCC2 (ASIC_BASE+0x03000084)#define DIDST2 (ASIC_BASE+0x03000088)#define DIDSTC2 (ASIC_BASE+0x0300008C)#define DCON2 (ASIC_BASE+0x03000090)#define DSTAT2 (ASIC_BASE+0x03000094)#define DCSRC2 (ASIC_BASE+0x03000098)#define DCDST2 (ASIC_BASE+0x0300009C)#define DMASKTRIG2 (ASIC_BASE+0x030000A0)#define DISRC3 (ASIC_BASE+0x030000C0)#define DISRCC3 (ASIC_BASE+0x030000C4)#define DIDST3 (ASIC_BASE+0x030000C8)#define DIDSTC3 (ASIC_BASE+0x030000CC)#define DCON3 (ASIC_BASE+0x030000D0)#define DSTAT3 (ASIC_BASE+0x030000D4)#define DCSRC3 (ASIC_BASE+0x030000D8)#define DCDST3 (ASIC_BASE+0x030000DC)#define DMASKTRIG3 (ASIC_BASE+0x030000E0)/*------------------------------------------------------------------ * CLOCK & POWER MANAGEMENT REGISTER DEFINITION *------------------------------------------------------------------*//* CLOCK & POWER Managment Registers Definition */#define LOCKTIME (ASIC_BASE+0x04000000)#define MPLLCON (ASIC_BASE+0x04000004)#define UPLLCON (ASIC_BASE+0x04000008)#define CLKCON (ASIC_BASE+0x0400000C)#define CLKSLOW (ASIC_BASE+0x04000010)#define CLKDIVN (ASIC_BASE+0x04000014)/* LOCKTIME (PLL lock time count Register) */#define bU_LTIME (0xfff<<12)#define bM_LTIME (0xfff)#define rLOCKTIME (bU_LTIME | bM_LTIME)/* PLLCON (PLL configuration Register) */#define FPLLin (12 * MHz) /******************************************* * bMMDIV : * (50-8) : 50 MHz * (100-8) : 100 MHz * (110-8) : 110 MHz * (130-8) : 130 MHz * (140-8) : 140 MHz * (160-8) : 160 MHz *******************************************///#define bMMDIV (100-8) /* 100MHz *///#define bMMDIV (200-8)//#define bMPDIV (0x4) //#define bMSDIV (0x1)/* 1 : 100/160... MHz, 2 : 50/80... MHz */#define bMMDIV 0xa1#define bMPDIV 0x3#define bMSDIV 0x1#define FMPLLout (((bMMDIV+8) * FPLLin) / ((bMPDIV+2) * 2))#define rMPLLCON (bMSDIV|(bMPDIV<<4)|(bMMDIV<<12))//#define rMPLLCON (0xa1 << 12 | 0x3 << 4 | 0x1) /* 202.8MHz */#define bUMDIV (48-8) /* 48MHz */#define bUPDIV (0x4) #define bUSDIV (0x1) #define FUPLLout (((bUMDIV+8) * FPLLin) / ((bUPDIV+2) * 2))#define rUPLLCON (bUSDIV|(bUPDIV<<4)|(bUMDIV<<12))/* CLKCON (Clock generator control Register) */#define bSPI (1<<15)#define bIIS (1<<14)#define bIIC (1<<13)#define bADC (1<<12)#define bRTC (1<<11)#define bGPIO (1<<10)#define bUART1 (1<<9)#define bUART0 (1<<8)#define bMMC (1<<7)#define bPWMTIMER (1<<6)#define bUSB_device (1<<5)#define bUSB_host (1<<4)#define bLCDC (1<<3)#define bIDLE_BIT (0<<2)#define bSL_IDLE (0<<1)#define bSTOP_BIT (0<<0)#define rCLKCON (bIIS|bIIC|bADC|bRTC|bGPIO|bUART1|bUART0|bMMC|bPWMTIMER|bUSB_device|bUSB_host|bLCDC)/* CLKSLOW (Slow clock control Register) */#define bUCLK_ON (0x80)#define bMPLL_OFF (0x20)#define bSLOW_BIT (0x10)#define bSLOW_VAL (0x4)#define rCLKSLOW (bSLOW_VAL)/* CLKDIVN (Clock divider control Register) */#define bHDIVN (1<<1)/* #define bPDIVN (0<<0) */#define bPDIVN (1<<0)#define rCLKDIVN (bHDIVN | bPDIVN)#define FCLK (MCLK)#define HCLK (FCLK/(bHDIVN))#define PCLK (HCLK/(1<<bPDIVN))/*------------------------------------------------------------------ * LCD CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*/#define LCDCON1 (ASIC_BASE+0x05000000)#define LCDCON2 (ASIC_BASE+0x05000004)#define LCDCON3 (ASIC_BASE+0x05000008)#define LCDCON4 (ASIC_BASE+0x0500000C)#define LCDCON5 (ASIC_BASE+0x05000010)#define LCDSADDR1 (ASIC_BASE+0x05000014)#define LCDSADDR2 (ASIC_BASE+0x05000018)#define LCDSADDR3 (ASIC_BASE+0x0500001C)#define REDLUT (ASIC_BASE+0x05000020)#define GREENLUT (ASIC_BASE+0x05000024)#define BLUELUT (ASIC_BASE+0x05000028)#define DP1_2 (ASIC_BASE+0x0500002C)#define DP4_7 (ASIC_BASE+0x05000030)#define DP3_5 (ASIC_BASE+0x05000034)#define DP2_3 (ASIC_BASE+0x05000038)#define DP5_7 (ASIC_BASE+0x0500003C)#define DP3_4 (ASIC_BASE+0x05000040)#define DP4_5 (ASIC_BASE+0x05000044)#define DP6_7 (ASIC_BASE+0x05000048)#define DITHMODE (ASIC_BASE+0x0500004C)#define TPAL (ASIC_BASE+0x05000050)#define LCDINTPND (ASIC_BASE+0x05000054)#define LCDSRCPND (ASIC_BASE+0x05000058)#define LCDINTMSK (ASIC_BASE+0x0500005C)#define LPCSEL (ASIC_BASE+0x05000060)#define PALETTE (ASIC_BASE+0x05000400)/*------------------------------------------------------------------ * NAND FLASH CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*/#define NFCONF (ASIC_BASE+0x06000000)#define NFCMD (ASIC_BASE+0x06000004)#define NFADDR (ASIC_BASE+0x06000008)#define NFDATA (ASIC_BASE+0x0600000C)#define NFSTAT (ASIC_BASE+0x06000010)#define NFECC (ASIC_BASE+0x06000014)#define NFECC0 (ASIC_BASE+0x06000014)#define NFECC1 (ASIC_BASE+0x06000015)#define NFECC2 (ASIC_BASE+0x06000016)/* NFCONF (NAND Flash Configuration Register) */#define bNFEN (1<<15)#define bECC_INIT (1<<12)#define bNFCE (1<<11)#define bTACLS (1<<8)#define bTWRPH0 (1<<4)#define bTWRPH1 (1<<0)#define rNFCONF (bNFEN|bECC_INIT|bTACLS|bTWRPH0|bTWRPH1)/* NFSTAT (NAND Flash Operation status Register) */#define bAUTOBOOT_DONE (1<<15)#define bCLE (1<<11)#define bALE (1<<10)#define bFRE (1<<9)#define bFWE (1<<8)#define bRnB (1<<0)/*------------------------------------------------------------------ * UART CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*//* Channel 0 */#define ULCON0 (ASIC_BASE+0x08000000)#define UCON0 (ASIC_BASE+0x08000004)#define UFCON0 (ASIC_BASE+0x08000008)#define UMCON0 (ASIC_BASE+0x0800000C)#define UTRSTAT0 (ASIC_BASE+0x08000010)#define UERSTAT0 (ASIC_BASE+0x08000014)#define UFSTAT0 (ASIC_BASE+0x08000018)#define UMSTAT0 (ASIC_BASE+0x0800001C)#ifdef BIG_ENDIAN#define UTXH0 (ASIC_BASE+0x08000023)#define URXH0 (ASIC_BASE+0x08000027)#else /* BIG_ENDIAN */#define UTXH0 (ASIC_BASE+0x08000020)#define URXH0 (ASIC_BASE+0x08000024)#endif /* LITTLE_ENDIAN */#define UBRDIV0 (ASIC_BASE+0x08000028)/* Channel 1 */#define ULCON1 (ASIC_BASE+0x08004000)#define UCON1 (ASIC_BASE+0x08004004)#define UFCON1 (ASIC_BASE+0x08004008)#define UMCON1 (ASIC_BASE+0x0800400C)#define UTRSTAT1 (ASIC_BASE+0x08004010)#define UERSTAT1 (ASIC_BASE+0x08004014)#define UFSTAT1 (ASIC_BASE+0x08004018)#define UMSTAT1 (ASIC_BASE+0x0800401C)#ifdef BIG_ENDIAN#define UTXH1 (ASIC_BASE+0x08004023)#define URXH1 (ASIC_BASE+0x08004027)#else /* BIG_ENDIAN */#define UTXH1 (ASIC_BASE+0x08004020)#define URXH1 (ASIC_BASE+0x08004024)#endif /* LITTLE_ENDIAN */#define UBRDIV1 (ASIC_BASE+0x08004028)/* Channel 2 */#define ULCON2 (ASIC_BASE+0x08008000)#define UCON2 (ASIC_BASE+0x08008004)#define UFCON2 (ASIC_BASE+0x08008008)#define UMCON2 (ASIC_BASE+0x0800800C)#define UTRSTAT2 (ASIC_BASE+0x08008010)#define UERSTAT2 (ASIC_BASE+0x08008014)#define UFSTAT2 (ASIC_BASE+0x08008018)#define UMSTAT2 (ASIC_BASE+0x0800801C)#ifdef BIG_ENDIAN#define UTXH2 (ASIC_BASE+0x08008023)#define URXH2 (ASIC_BASE+0x08008027)#else /* BIG_ENDIAN */#define UTXH2 (ASIC_BASE+0x08008020)#define URXH2 (ASIC_BASE+0x08008024)#endif /* LITTLE_ENDIAN */#define UBRDIV2 (ASIC_BASE+0x08008028)/*------------------------------------------------------------------ * PWM TIMER REGISTER DEFINITION *------------------------------------------------------------------*/#define TCFG0 (ASIC_BASE+0x09000000)#define TCFG1 (ASIC_BASE+0x09000004)#define TCON (ASIC_BASE+0x09000008)#define TCNTB0 (ASIC_BASE+0x0900000C)#define TCMPB0 (ASIC_BASE+0x09000010)#define TCNTO0 (ASIC_BASE+0x09000014)#define TCNTB1 (ASIC_BASE+0x09000018)#define TCMPB1 (ASIC_BASE+0x0900001C)#define TCNTO1 (ASIC_BASE+0x09000020)#define TCNTB2 (ASIC_BASE+0x09000024)#define TCMPB2 (ASIC_BASE+0x09000028)#define TCNTO2 (ASIC_BASE+0x0900002C)#define TCNTB3 (ASIC_BASE+0x09000030)#define TCMPB3 (ASIC_BASE+0x09000034)#define TCNTO3 (ASIC_BASE+0x09000038)#define TCNTB4 (ASIC_BASE+0x0900003C)#define TCNTO4 (ASIC_BASE+0x09000040)/*----------------------------------------------------------------- * WATCH-DOG TIMER REGISTER DEFINITION *------------------------------------------------------------------*/#define WTCON (ASIC_BASE+0x0B000000)#define WTDAT (ASIC_BASE+0x0B000004)#define WTCNT (ASIC_BASE+0x0B000008)#define bWTCON8 (0<<8) /* Prescaler value : 0 ~ 255 */#define bWTCON5 (0<<5) /* 0 : Disable, 1 : Enable */#define bWTCON3 (0<<3) /* Clock division(0:16, 1:32, 2:64, 3:128) */#define bWTCON2 (0<<2) /* Interrupt mode(0:Disable, 1:Enable) */#define bWTCON0 (0<<0) /* Reset output(0:Disable, 1:Enable) */#define rWTCON (bWTCON8|bWTCON5|bWTCON3|bWTCON2|bWTCON0)/*------------------------------------------------------------------ * USB DEVICE CONTROLLER REGISTER DEFINITION *------------------------------------------------------------------*/#ifdef BIG_ENDIAN#define FUNC_ADDR_REG (ASIC_BASE+0x0A000143)#define PWR_REG (ASIC_BASE+0x0A000147)#define EP_INT_REG (ASIC_BASE+0x0A00014B)#define USB_INT_REG (ASIC_BASE+0x0A00015B)#define EP_INT_EN_REG (ASIC_BASE+0x0A00015F)#define USB_INT_EN_REG (ASIC_BASE+0x0A00016F)#define FRAME_NUM1_REG (ASIC_BASE+0x0A000173)#define INDEX_REG (ASIC_BASE+0x0A00017B)#define EP0_CSR (ASIC_BASE+0x0A000187)#define IN_CSR1_REG (ASIC_BASE+0x0A000187)#define IN_CSR2_REG (ASIC_BASE+0x0A00018B)#define MAXP_REG (ASIC_BASE+0x0A00018F)#define OUT_CSR1_REG (ASIC_BASE+0x0A000193)#define OUT_CSR2_REG (ASIC_BASE+0x0A000197)#define OUT_FIFO_CNT1_REG (ASIC_BASE+0x0A00019B)#define OUT_FIFO_CNT2_REG (ASIC_BASE+0x0A00019F)#define EP0_FIFO (ASIC_BASE+0x0A0001C3)#define EP1_FIFO (ASIC_BASE+0x0A0001C7)⌨️ 快捷键说明
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