s3c2410x.h

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#ifndef __S3C2410_H
#define __S3C2410_H

/*-------------------------------------------------------------------
 *  Processor Mode and Mask
 *
 *  Format of the Program Status Register
 *
 *  31  30  29   28         7   6   5   4   3   2   1   0
 * +---+---+---+---+--ss--+---+---+---+---+---+---+---+---+
 * | N | Z | C | V |      | I | F | T |     M4 ~ M0       |
 * +---+---+---+---+--ss--+---+---+---+---+---+---+---+---+
 *
 */
#define FBit            0x40
#define IBit            0x80
#define LOCKOUT         0xc0    /* Interrupt lockout value */
#define LOCK_MSK        0xc0    /* Interrupt lockout mask value */
#define MODE_MASK       0x1f    /* Processor Mode Mask */
#define UDF_MODE        0x1b    /* Undefine Mode(UDF) */
#define ABT_MODE        0x17    /* Abort Mode(ABT) */
#define SUP_MODE        0x13    /* Supervisor Mode (SVC) */
#define IRQ_MODE        0x12    /* Interrupt Mode (IRQ) */
#define FIQ_MODE        0x11    /* Fast Interrupt Mode (FIQ) */
#define USR_MODE        0x10    /* User Mode(USR) */


/*-------------------------------------------------------------------
 * Define S3C2410X CPU master clock
 *------------------------------------------------------------------*/
#define MHz 		(1000000)
#define MCLK	   	(FMPLLout)	/* Refer to PLLCON register setting */
/* #define HZ		(MCLK/MHz) */

#define ASIC_BASE       (0x48000000)

#define VPint    *(volatile unsigned int *)
#define VPshort  *(volatile unsigned short *)
#define VPchar   *(volatile unsigned char *)

/*-------------------------------------------------------------------
 * Read and write control and status registers 
 * User must have to use this function
 * CSR_READ   : Read word (4 bytes : 32 bit)
 * CSR_WRITE  : Write word (4 bytes : 32 bit)
 * CSRH_READ  : Read half word (2 bytes : 16 bit)
 * CSRH_WRITE : Write half word (2 bytes : 16 bit)
 * CSRB_READ  : Read byte (1 byte : 8 bit)
 * CSRB_WRITE : Write byte (1 byte : 8 bit)
 *------------------------------------------------------------------*/
#ifndef CSR_WRITE
#define CSR_WRITE(addr,data) (VPint(addr) = (data))
#else
#define CSR_WRITE(addr,data) __raw_writel((data), VPint(addr))
#endif

#ifndef CSR_READ
#define CSR_READ(addr)       (VPint(addr))
#else
#define CSR_READ(addr)       __raw_readl(VPint(addr))
#endif

#ifndef CSRH_WRITE
#define CSRH_WRITE(addr,data) (VPshort(addr) = (data))
#endif

#ifndef CSRH_READ
#define CSRH_READ(addr)       (VPshort(addr))
#endif

#ifndef CSRB_WRITE
#define CSRB_WRITE(addr,data) (VPchar(addr) = (data))
#endif

#ifndef CSRB_READ
#define CSRB_READ(addr)       (VPchar(addr))
#endif

/* -----------------------------------------------------------------
 * MEMORY CONTROLLER REGISTER DEFINITION
 *------------------------------------------------------------------*/
#define BWSCON  		(ASIC_BASE+0x0000000)
#define BANKCON0  		(ASIC_BASE+0x0000004)
#define BANKCON1  		(ASIC_BASE+0x0000008)
#define BANKCON2  		(ASIC_BASE+0x000000C)
#define BANKCON3  		(ASIC_BASE+0x0000010)
#define BANKCON4  		(ASIC_BASE+0x0000014)
#define BANKCON5  		(ASIC_BASE+0x0000018)
#define BANKCON6  		(ASIC_BASE+0x000001C)
#define BANKCON7  		(ASIC_BASE+0x0000020)
#define REFRESH  		(ASIC_BASE+0x0000024)
#define BANKSIZE  		(ASIC_BASE+0x0000028)
#define MRSRB6	 		(ASIC_BASE+0x000002C)
#define MRSRB7	 		(ASIC_BASE+0x0000030)

#define SYS_INIT_BASE	BWSCON

/* BWSCON (Bus width & Wait Status control Register) */
#define	bST7	(0<<31) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS7	(0<<30) /* 0: WAIT disable, 1: WAIT enable */
#define bDW7	(2<<28) /* Not used -> 0: 8bit, 1: 16bit, 2: 32bit */

#define	bST6	(0<<27) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS6	(0<<26) /* 0: WAIT disable, 1: WAIT enable */
#define bDW6	(2<<24) /* SDRAM -> 0: 8bit, 1: 16bit, 2: 32bit */

#define	bST5	(0<<23) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS5	(0<<22) /* 0: WAIT disable, 1: WAIT enable */
#define bDW5	(1<<20) /* Not used -> 0: 8bit, 1: 16bit, 2: 32bit */

#define	bST4	(0<<19) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS4	(0<<18) /* 0: WAIT disable, 1: WAIT enable */
#define bDW4	(1<<16) /* Not used -> 0: 8bit, 1: 16bit, 2: 32bit */

#define	bST3	(0<<15) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS3	(1<<14) /* 0: WAIT disable, 1: WAIT enable */
#define bDW3	(1<<12) /* Ethernet -> 0: 8bit, 1: 16bit, 2: 32bit */

#define	bST2	(0<<11) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS2	(0<<10) /* 0: WAIT disable, 1: WAIT enable */
#define bDW2	(1<<8)  /* Not used -> 0: 8bit, 1: 16bit, 2: 32bit */

#define	bST1	(0<<11) /* 0: unused UB/LB, 1: used UB/LB */
#define	bWS1	(0<<10) /* 0: WAIT disable, 1: WAIT enable */
#define bDW1	(2<<4)  /* Intel Flash -> 0: 8bit, 1: 16bit, 2: 32bit */

#define bDW0	(1<<1)  /* ROM -> 1: 16bit, 2: 32bit */
#define bENDIAN	(0<<0)  /* 0: Little Endian, 1: Big Endian */

#define rBWSCON (bENDIAN|bDW0|bDW1|bDW2|bDW3|bDW4|bDW5|bDW6|bDW7|bWS1|  \
                bWS2|bWS3|bWS4|bWS5|bWS6|bWS7|bST1|bST2|bST3|bST4|bST5| \
                bST6|bST7)

/* BANKCON0 (Bank0 control Register) */
#define bTacs0	(0<<13) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcos0	(0<<11) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacc0	(7<<8) 	/* 0=1clks, 1=2clks, 2=3clks,  3=4clks */
 		       	       	/* 4=6clks, 5=8clks, 6=10clks, 7=14clks */
#define bTcoh0	(0<<6) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcah0	(0<<4) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacp0	(0<<2) 	/* 0=2clks, 1=3clks, 2=4clks, 3=6clks */
#define bPMC0	(0<<0) 	/* 0=Normal, 1=4-data, 2=8-data, 3=16-data */

#define rBANKCON0 (bPMC0|bTacp0|bTcah0|bTcoh0|bTacc0|bTcos0|bTacs0)

/* BANKCON1 (Bank1 control Register) */
#define bTacs1	(0<<13) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcos1	(0<<11) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacc1	(7<<8) 	/* 0=1clks, 1=2clks, 2=3clks,  3=4clks */
   	       	       		/* 4=6clks, 5=8clks, 6=10clks, 7=14clks */
#define bTcoh1	(0<<6) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcah1	(0<<4) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacp1	(0<<2) 	/* 0=2clks, 1=3clks, 2=4clks, 3=6clks */
#define bPMC1	(0<<0) 	/* 0=Normal, 1=4-data, 2=8-data, 3=16-data */

#define rBANKCON1 (bPMC1|bTacp1|bTcah1|bTcoh1|bTacc1|bTcos1|bTacs1)

/* BANKCON2 (Bank2 control Register) */
#define bTacs2	(0<<13) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcos2	(0<<11) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacc2	(7<<8) 	/* 0=1clks, 1=2clks, 2=3clks,  3=4clks */
   	       	       		/* 4=6clks, 5=8clks, 6=10clks, 7=14clks */
#define bTcoh2	(0<<6) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcah2	(0<<4) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacp2	(0<<2) 	/* 0=2clks, 1=3clks, 2=4clks, 3=6clks */
#define bPMC2	(0<<0) 	/* 0=Normal, 1=4-data, 2=8-data, 3=16-data */

#define rBANKCON2 (bPMC2|bTacp2|bTcah2|bTcoh2|bTacc2|bTcos2|bTacs2)

/* BANKCON3 (Bank3 control Register) */
#define bTacs3	(3<<13) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcos3	(3<<11) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacc3	(7<<8) 	/* 0=1clks, 1=2clks, 2=3clks,  3=4clks */
           	       		/* 4=6clks, 5=8clks, 6=10clks, 7=14clks */
#define bTcoh3	(3<<6) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcah3	(3<<4) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacp3	(3<<2) 	/* 0=2clks, 1=3clks, 2=4clks, 3=6clks */
#define bPMC3	(0<<0) 	/* 0=Normal, 1=4-data, 2=8-data, 3=16-data */

#define rBANKCON3 (bPMC3|bTacp3|bTcah3|bTcoh3|bTacc3|bTcos3|bTacs3)

/* BANKCON4 (Bank4 control Register) */
#define bTacs4	(0<<13) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcos4	(0<<11) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacc4	(7<<8) 	/* 0=1clks, 1=2clks, 2=3clks,  3=4clks */
           	       		/* 4=6clks, 5=8clks, 6=10clks, 7=14clks */
#define bTcoh4	(0<<6) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcah4	(0<<4) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacp4	(0<<2)	/* 0=2clks, 1=3clks, 2=4clks, 3=6clks */
#define bPMC4	(0<<0) 	/* 0=Normal, 1=4-data, 2=8-data, 3=16-data */

#define rBANKCON4 (bPMC4|bTacp4|bTcah4|bTcoh4|bTacc4|bTcos4|bTacs4)

/* BANKCON5 (Bank5 control Register) */
#define bTacs5	(0<<13) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcos5	(0<<11) /* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacc5	(7<<8) 	/* 0=1clks, 1=2clks, 2=3clks,  3=4clks */
           	       		/* 4=6clks, 5=8clks, 6=10clks, 7=14clks */
#define bTcoh5	(0<<6) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTcah5	(0<<4) 	/* 0=0clks, 1=1clks, 2=2clks, 3=4clks */
#define bTacp5	(0<<2) 	/* 0=2clks, 1=3clks, 2=4clks, 3=6clks */
#define bPMC5	(0<<0) 	/* 0=Normal, 1=4-data, 2=8-data, 3=16-data */

#define rBANKCON5 (bPMC5|bTacp5|bTcah5|bTcoh5|bTacc5|bTcos5|bTacs5)

/* BANKCON6 (Bank6 control Register) */
#define bMT6	(3<<15) /* 0=ROM/SRAM, 1=FPAGE, 2=EDO, 3=SDRAM */
#define bTrcd6 	(1<<2) 	/* 0=2clks, 1=3clks, 2=4clks */
#define bCAN6 	(1<<0) 	/* 0=8bit, 1=9bit, 2=10bit */

#define rBANKCON6 (bCAN6|bTrcd6|bMT6)

/* BANKCON7 (Bank7 control Register) */
#define bMT7	(3<<15) /* 0=ROM/SRAM, 1=FPAGE, 2=EDO, 3=SDRAM */
#define bTrcd7 	(1<<2) 	/* 0=2clks, 1=3clks, 2=4clks */
#define bCAN7 	(1<<0) 	/* 0=8bit, 1=9bit, 2=10bit */

#define rBANKCON7 (bCAN7|bTrcd7|bMT7)

/* REFRESH (DRAM/SDRAM refresh control Register) */
#define bREFEN	(1<<23) /* 0=Disable, 1=Enable */
#define bTREFMD	(0<<22) /* 0=CBR/Auto refresh, 1=Self refresh */
#define bTrp	(0<<20) /* 0=2clks, 1=3clks, 2=4clks */
#define bTrc	(3<<18) /* 0=4clks, 1=5clks, 2=6clks, 3=7clks */
#define bREFCNT	(2049-((HCLK/(MHz*10))*156)) /* period=15.6us */

#define rREFRESH (bREFEN|bTREFMD|bTrp|bTrc|bREFCNT)

/* BANKSIZE (Flexible bank size Register) */
#define bSCLKE_EN	(1<<5) /* SDRAM Power down mode : 0=Disable, 1=Enable */
#define bSCLK_EN	(1<<4) /* SDRAM SCLK Enable : 0=always, 1=access only */
#define bBK76MAP	(0<<0) /* 0=32M, 1=64M, 2=128M, 4=2M, 5=4M, 6=8M, 7=16M */

#define rBANKSIZE (bSCLKE_EN|bSCLK_EN|bBK76MAP)

/* MRSRB6 (Mode register set register bank6) */
#define bWBL6	(0<<9) /* Write burst length : Recommended by 0 */
#define bTM6	(0<<7) /* 0=mode register set, 1=2=3=reserved */
#define bCL6	(2<<4) /* CAS latency : 0=1clk, 2=2clks, 3=3clks */
#define bBT6	(0<<3) /* Burst type : 0=Sequential, 1=N/A */
#define bBL6	(0<<0) /* Burst length : 0=1, others=N/A */

#define rMRSRB6 (bWBL6|bTM6|bCL6|bBT6|bBL6)

/* MRSRB7 (Mode register set register bank7) */
#define bWBL7	(0<<9) /* Write burst length : Recommended by 0 */
#define bTM7	(0<<7) /* 0=mode register set, 1=2=3=reserved */
#define bCL7	(2<<4) /* CAS latency : 0=1clk, 2=2clks, 3=3clks */
#define bBT7	(0<<3) /* Burst type : 0=Sequential, 1=N/A */
#define bBL7	(0<<0) /* Burst length : 0=1, others=N/A */

#define rMRSRB7 (bWBL7|bTM7|bCL7|bBT7|bBL7)


/*------------------------------------------------------------------
 * USB HOST CONTROLLER REGISTER DEFINITION
 *------------------------------------------------------------------*/
#define	HcRevision			(ASIC_BASE+0x01000000)
#define	HcControl			(ASIC_BASE+0x01000004)
#define	HcCommonStatus		(ASIC_BASE+0x01000008)
#define	HcInterruptStatus	(ASIC_BASE+0x0100000C)
#define	HcInterruptEnable	(ASIC_BASE+0x01000010)
#define	HcInterruptDisable	(ASIC_BASE+0x01000014)
#define	HcHCCA				(ASIC_BASE+0x01000018)
#define	HcPeriodCuttentED	(ASIC_BASE+0x0100001C)
#define	HcControlHeadED		(ASIC_BASE+0x01000020)
#define	HcControlCurrentED	(ASIC_BASE+0x01000024)
#define	HcBulkHeadED		(ASIC_BASE+0x01000028)
#define	HcBulkCurrentED		(ASIC_BASE+0x0100002C)
#define	HcDoneHead			(ASIC_BASE+0x01000030)
#define	HcRmInterval		(ASIC_BASE+0x01000034)
#define	HcFmRemaining		(ASIC_BASE+0x01000038)
#define	HcFmNumber			(ASIC_BASE+0x0100003C)
#define	HcPeriodicStart		(ASIC_BASE+0x01000040)
#define	HcLSThreshold		(ASIC_BASE+0x01000044)
#define	HcRhDescriptorA		(ASIC_BASE+0x01000048)
#define	HcRhDescriptorB		(ASIC_BASE+0x0100004C)
#define	HcRhStatus			(ASIC_BASE+0x01000050)
#define	HcRhPortStatus1		(ASIC_BASE+0x01000054)
#define	HcRhPortStatus2		(ASIC_BASE+0x01000058)


/*------------------------------------------------------------------
 * INTERRUPT CONTROLLER REGISTER DEFINITION
 *------------------------------------------------------------------*/
#define SRCPND  		(ASIC_BASE+0x02000000)
#define INTMOD 			(ASIC_BASE+0x02000004)
#define INTMSK 			(ASIC_BASE+0x02000008)
#define PRIORITY		(ASIC_BASE+0x0200000C)
#define INTPND 			(ASIC_BASE+0x02000010)
#define INTOFFSET		(ASIC_BASE+0x02000014)
#define SRCSUBPND		(ASIC_BASE+0x02000018)
#define INTSUBMSK		(ASIC_BASE+0x0200001C)


/*------------------------------------------------------------------
 * DMA CONTROLLER REGISTER DEFINITION
 *------------------------------------------------------------------*/