vec.s
来自「ADS下的bios工程」· S 代码 · 共 249 行
S
249 行
#include <bios/s3c2410x.h>#include <bios/linkage.h>/*------------------------------------------------------ * Define exception table location *------------------------------------------------------*/#define loc_reset_vector (RESET_SDRAM_BASE)#define loc_undef_vector (RESET_SDRAM_BASE + 4)#define loc_swi_vector (RESET_SDRAM_BASE + 8)#define loc_prefetch_vector (RESET_SDRAM_BASE + 12)#define loc_abort_vector (RESET_SDRAM_BASE + 16)#define loc_reserv_vector (RESET_SDRAM_BASE + 20)#define loc_irq_vector (RESET_SDRAM_BASE + 24)#define loc_fiq_vector (RESET_SDRAM_BASE + 28)/*------------------------------------------------------ * Vectered Interrupt exception table location *------------------------------------------------------*/#define loc_eint0_vector (RESET_SDRAM_BASE + 32)#define loc_eint1_vector (RESET_SDRAM_BASE + 36)#define loc_eint2_vector (RESET_SDRAM_BASE + 40)#define loc_eint3_vector (RESET_SDRAM_BASE + 44)#define loc_eint4_vector (RESET_SDRAM_BASE + 48)#define loc_eint5_vector (RESET_SDRAM_BASE + 52)#define loc_eint6_vector (RESET_SDRAM_BASE + 56)#define loc_eint7_vector (RESET_SDRAM_BASE + 60)#define loc_tick_vector (RESET_SDRAM_BASE + 64)#define loc_wdt_vector (RESET_SDRAM_BASE + 68)#define loc_timer0_vector (RESET_SDRAM_BASE + 72)#define loc_timer1_vector (RESET_SDRAM_BASE + 76)#define loc_timer2_vector (RESET_SDRAM_BASE + 80)#define loc_timer3_vector (RESET_SDRAM_BASE + 84)#define loc_timer4_vector (RESET_SDRAM_BASE + 88)#define loc_uerr_vector (RESET_SDRAM_BASE + 92)#define loc_reserverd_vector (RESET_SDRAM_BASE + 96)#define loc_dma0_vector (RESET_SDRAM_BASE + 100)#define loc_dma1_vector (RESET_SDRAM_BASE + 104)#define loc_dma2_vector (RESET_SDRAM_BASE + 108)#define loc_dma3_vector (RESET_SDRAM_BASE + 112)#define loc_mmc_vector (RESET_SDRAM_BASE + 116)#define loc_spi_vector (RESET_SDRAM_BASE + 120)#define loc_urxd0_vector (RESET_SDRAM_BASE + 124)#define loc_urxd1_vector (RESET_SDRAM_BASE + 128)#define loc_usbd_vector (RESET_SDRAM_BASE + 132)#define loc_usbh_vector (RESET_SDRAM_BASE + 136)#define loc_iic_vector (RESET_SDRAM_BASE + 140)#define loc_utxd0_vector (RESET_SDRAM_BASE + 144)#define loc_utxd1_vector (RESET_SDRAM_BASE + 148)#define loc_rtc_vector (RESET_SDRAM_BASE + 152)#define loc_adc_vector (RESET_SDRAM_BASE + 156)/*------------------------------------------------------ * Define exception stack area *------------------------------------------------------*/#define FIQ_STACK_SIZE 0x0000400#define PREFE_STACK_SIZE 0x0000400#define ABORT_STACK_SIZE 0x0000400#define UNDEF_STACK_SIZE 0x0000400#define IRQ_STACK_SIZE 0x0004000#define SVC_STACK_SIZE 0x0010000#define FIQ_STACK_BASE (SYMBOL_NAME(_end) + FIQ_STACK_SIZE)#define PREFE_STACK_BASE (FIQ_STACK_BASE + PREFE_STACK_SIZE)#define ABORT_STACK_BASE (PREFE_STACK_BASE + ABORT_STACK_SIZE)#define UNDEF_STACK_BASE (ABORT_STACK_BASE + UNDEF_STACK_SIZE)#define IRQ_STACK_BASE (UNDEF_STACK_BASE + IRQ_STACK_SIZE)#define SVC_STACK_BASE (IRQ_STACK_BASE + SVC_STACK_SIZE) .text/*------------------------------------------------------ * Useful macro for IRQ *------------------------------------------------------*/ .macro get_irqnr, irqnr, base ldr \base, =INTPND ldr \base, [\base] mov \irqnr, #00: movs \base, \base, lsr #1 bcs 1f add \irqnr, \irqnr, #1 b 0b1: .endm /*------------------------------------------------------ * Setup stack and exception vector *------------------------------------------------------*/ENTRY(vec_init) /* setup stack pointer */ mrs r0, cpsr bic r0, r0, #LOCKOUT | MODE_MASK orr r2, r0, #SUP_MODE @ exception undef stack orr r1, r0, #LOCKOUT | UDF_MODE msr cpsr, r1 msr spsr, r2 ldr sp, =UNDEF_STACK_BASE @ exception abort stack orr r1, r0, #LOCKOUT | ABT_MODE msr cpsr, r1 msr spsr, r2 ldr sp, =ABORT_STACK_BASE @ exception irq stack orr r1, r0, #LOCKOUT | IRQ_MODE msr cpsr, r1 msr spsr, r2 ldr sp, =IRQ_STACK_BASE @ exception fiq stack orr r1, r0, #LOCKOUT | FIQ_MODE msr cpsr, r1 msr spsr, r2 ldr sp, =FIQ_STACK_BASE orr r1, r0, #LOCKOUT | SUP_MODE msr cpsr, r1 ldr sp, =SVC_STACK_BASE /* setup exception vector table */ ldr r0, =loc_reset_vector ldr r1, =L_Exception_Vector_Table mov r2, #81: ldr r3, [r1], #4 str r3, [r0], #4 subs r2, r2, #1 bne 1b mov pc, lr /* return *//*------------------------------------------------------ * Low level hardware exception handler *------------------------------------------------------*/ENTRY (undef_handler) ldr r13, =loc_undef_vector ldr r13, [r13] mov pc, r13ENTRY(swi_handler) b system_swi_handler#if 0 sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =loc_swi_vector ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc}#endifENTRY(prefetch_handler) ldr r13, =loc_prefetch_vector ldr r13, [r13] mov pc, r13ENTRY(abort_handler) ldr r13, =loc_abort_vector ldr r13, [r13] mov pc, r13ENTRY(irq_handler) ldr r13, =loc_irq_vector ldr r13, [r13] mov pc, r13ENTRY(fiq_handler) sub sp, sp, #4 stmfd sp!, {r0} ldr r0, =loc_fiq_vector ldr r0, [r0] str r0, [sp, #4] ldmfd sp!, {r0, pc}/*------------------------------------------------------ * System exception handler *------------------------------------------------------*/system_undef_handler : ldr sp, =UNDEF_STACK_BASE stmfd sp!, {r0-r12, lr} mrs r0, spsr mov r1, sp@ bl SYMBOL_NAME(Undef_action) ldmfd sp!, {r0-r12, pc}^system_swi_handler : stmfd sp!, {r0-r12, lr} ldr r3, [lr, #-4] bic r3, r3, #0xff000000@ bl SYMBOL_NAME(swi_action) ldmfd sp!, {r0-r12, pc}system_prefetch_handler : ldr sp, =PREFE_STACK_BASE stmfd sp!, {r0-r12, lr} mrs r0, spsr mov r1, sp@ bl SYMBOL_NAME(Pabort_action) ldmfd sp!, {r0-r12, lr} subs pc, lr, #4system_abort_handler : ldr sp, =ABORT_STACK_BASE stmfd sp!, {r0-r12, lr} mrs r0, spsr mov r1, sp@ bl SYMBOL_NAME(Dabort_action) ldmfd sp!, {r0-r12, lr} subs pc, lr, #8system_reserv_handler : sub pc, lr, #4system_irq_handler : ldr sp, =IRQ_STACK_BASE stmfd sp!, {r0-r12, lr} get_irqnr r0, r1@ bl SYMBOL_NAME(do_IRQ) @ brantch to IRQ service routine ldmfd sp!, {r0-r12, lr} subs pc, lr, #4system_fiq_handler : ldr sp, =FIQ_STACK_BASE stmfd sp!, {r0-r7, lr} mrs r0, spsr mov r1, sp@ bl SYMBOL_NAME(FIQ_action) ldmfd sp!, {r0-r7, lr} subs pc, lr, #4/*------------------------------------------------------ * Define exception table *------------------------------------------------------*/ .align 4L_Exception_Vector_Table : .long PHYS_SDRAM_BASE .long system_undef_handler .long system_swi_handler .long system_prefetch_handler .long system_abort_handler .long system_reserv_handler .long system_irq_handler .long system_fiq_handler
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