crt0.s

来自「ADS下的bios工程」· S 代码 · 共 191 行

#include <bios/s3c2410x.h>
#include <bios/linkage.h>

	.text

	.macro  spr_load   src, dst
	ldr	r0, =\dst
	ldr	r1, =\src
	str	r1, [r0]
	.endm

@ Entry
	.globl	_entry
_entry:
	b	reset_handler
	b	undef_handler
	b	swi_handler
	b	prefetch_handler
	b	abort_handler
	nop
	b	irq_handler
	b	fiq_handler

reset_handler :
	spr_load rWTCON, WTCON

	spr_load INT_MASK_DIS, INTMSK
	spr_load INT_MASK_DIS, INTSUBMSK

	spr_load rLOCKTIME, LOCKTIME

	spr_load rMPLLCON, MPLLCON
	spr_load rUPLLCON, UPLLCON

	/* FCLK = 100MHz, HCLK = FCLK/2, PCLK = FCLK/2 */
	/* FCLK = 200MHz, HCLK = FCLK/2, PCLK = FCLK/4 */
	spr_load rCLKDIVN, CLKDIVN

	spr_load 0x7fffff, GPACON
	spr_load 0x044555, GPBCON
	spr_load 0x7ff, GPBUP
	spr_load 0xaaaa56aa, GPCCON
	spr_load 0xffff, GPCUP
	spr_load 0xaaaaaaaa, GPDCON
	spr_load 0xffff, GPDUP
	spr_load 0xaaaaaaaa, GPECON
	spr_load 0xffff, GPEUP
	spr_load 0xaaaa, GPFCON
	spr_load 0xff, GPFUP
	spr_load 0xffddfff9, GPGCON
	spr_load 0xffff, GPGUP
	spr_load 0x2afaaa, GPHCON
	spr_load 0x7ff, GPHUP

	spr_load 0x22222222, EXTINT0
	spr_load 0x22222222, EXTINT1
	spr_load 0x22222222, EXTINT2

	bl	dbg_init
#ifdef DEBUG

	mov 	r0,#'\n'
	bl	printch

	mov 	r0,#'L'
	bl	printch
#endif
	mrs	r0, cpsr
	bic	r0, r0, #MODE_MASK
	orr	r0, r0, #SUP_MODE | IBit | FBit
	msr	cpsr, r0
#ifdef DEBUG
	mov 	r0,#'i'
	bl	printch

	mov	r0, #'a'
	bl	printch
	mov	r0, #'o'
	bl	printch
#endif

/* ROM and DRAM Configuration(Multiple Load and Store) */
        @Set memory control registers
	adr	r0, .L_DRAM_SysInitData_Reset
	ldr	r1, =SYS_INIT_BASE
        add     r2, r0, #52     @End address of SMRDATA
0:
        ldr     r3, [r0], #4
        str     r3, [r1], #4
        cmp     r2, r0
        bne     0b

#ifdef DEBUG
	mov 	r0,#'a'
	bl	printch
#endif

.L_clear_bss_section :
	mov	r0, #0
	ldr	r1, =SYMBOL_NAME(_bss_start)
	ldr	r2, =SYMBOL_NAME(_bss_end)
1:	str	r0, [r1], #4
	cmp	r1, r2
	blt	1b

#ifdef DEBUG
	mov 	r0,#'o'
	bl	printch
#endif

	bl      vec_init

	@ldr	r13, =0x1000

	@ldr	r0, =SYMBOL_NAME(_end)
	@mrc     p15, 0, r0, c1, c0, 0
	bl	SYMBOL_NAME(start_boot)
	b	.

	.ltorg

	.macro  addruart,rx
	ldr     \rx, =DEBUG_TX_BUFF_BASE
	.endm

	.macro  senduart,rd,rx
	strb     \rd, [\rx]
	.endm

	.macro  busyuart,rd,rx
1001:
	ldr     \rx, =DEBUG_CHK_STAT_BASE
	ldr     \rd, [\rx]
	and     \rd, \rd, #DEBUG_TX_DONE_CHECK_BIT
	teq     \rd, #DEBUG_TX_DONE_CHECK_BIT
	bne     1001b
	.endm

	.macro  waituart,rd,rx
	.endm

ENTRY(dbg_init)
	spr_load DEBUG_UMCON_REG_VAL, DEBUG_UARTMCON_BASE
	spr_load DEBUG_UFCON_REG_VAL, DEBUG_UARTFCON_BASE
	spr_load DEBUG_ULCON_REG_VAL, DEBUG_UARTLCON_BASE
	spr_load DEBUG_UCONT_REG_VAL, DEBUG_UARTCONT_BASE
	spr_load DEBUG_UBAUD_REG_VAL, DEBUG_UARTBAUD_BASE

	mov	pc, lr

#ifdef DEBUG
ENTRY(printascii)
	addruart r3
	b       2f
1:
	waituart r2, r3
	senduart r1, r3
	busyuart r2, r3
	teq     r1, #'\n'
	moveq   r1, #'\r'
	beq     1b
2:	teq     r0, #0
	ldrneb  r1, [r0], #1
	teqne   r1, #0
	bne     1b
	mov     pc, lr

ENTRY(printch)
	addruart r3
	mov     r1, r0
	mov     r0, #0
	b       1b
#endif

	.align 4

.L_DRAM_SysInitData_Reset:
	.long	rBWSCON
	.long	rBANKCON0
	.long	rBANKCON1
	.long	rBANKCON2
	.long	rBANKCON3
	.long	rBANKCON4
	.long	rBANKCON5
	.long	rBANKCON6
	.long	rBANKCON7
	.long	rREFRESH
	.long	rBANKSIZE
	.long	rMRSRB6
	.long	rMRSRB7