cs8900.c

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#include <bios/s3c2410x.h>
#include <bios/netdev.h>
#include <bios/time.h> 
#include <bios/stdio.h> 
#include <bios/types.h> 
#include <bios/system.h> 

#undef DEBUG_CS8900
#ifdef DEBUG_CS8900
#define DEBUG_MAC(fmt, args...) printf("%s-%s()[%d]: " fmt, \
      __FILE__, __FUNCTION__, __LINE__, args)
#else
#define DEBUG_MAC(fmt, args...)
#endif

/* 
 * General I/O port for CS8900 Device control 
 * ExINT0/GPG0 of S3C44B0 is assigned to IRQ0 of ISA I/F
 */
#define INT_CS8900		INT_EINT8	/* GPG1->EINT9 */
#define CS8900_IRQ_NUM		0		/* INTRQ0 */

/* CS8900A Device structure */
struct ei_device {
        struct net_device_stats stats;/* ethernet status field */
        int send_cmd;           /* the propercommand used to send a packet. */
        int isa_config;
        int irq_map;
        int rx_mode;
        int curr_rx_cfg;
        int linectl;
        int send_underrun;      /* keep track of how many underruns in a row we get */
	int no;			/* yskim dummy number 2001-02-15 */
        //struct sk_buff *skb;
};

static struct ei_device ei_local;

/* 
 * CS8900A register definition 
 * -------------------------------
 */
#define CS8900_MEM_BASE		(RESET_CS8900_BASE + (0x1<<12))
#define CS8900_IO_BASE		(RESET_CS8900_BASE)

#define PP_ChipID               0x0000 /*  offset 0h -> Corp -ID */
#define PP_ProdID               0x0002 /*  offset 2h -> Prod -ID */
#define PP_IOBASE               0x0020 /*  IO base address */
#define PP_INTNUM	        0x0022 /*  ISA interrupt select */
#define PP_DMACH	        0x0024 /*  ISA Rec DMA channel */
#define PP_ISASOF               0x0026 /*  ISA DMA offset */
#define PP_DmaFrameCnt          0x0028 /*  ISA DMA Frame count */
#define PP_DmaByteCnt           0x002A /*  ISA DMA Byte count */
#define PP_MEMBASE              0x002C /*  Memory base */
#define PP_ISABootBase          0x0030 /*  Boot Prom base  */
#define PP_ISABootMask          0x0034 /*  Boot Prom Mask */
#define PP_RxFrameByteCNT	0x0050 /*  Receive Frame Byte Counter */

#define PP_RxCFG                0x0102  /*  Rx Bus config */
#define PP_RxCTL                0x0104  /*  Receive Control Register */
#define PP_TxCFG                0x0106  /*  Transmit Config Register */
#define PP_TxCMD                0x0108  /*  Transmit Command Register */
#define PP_BufCFG               0x010A  /*  Bus configuration Register */
#define PP_LineCTL              0x0112  /*  Line Config Register */
#define PP_SelfCTL              0x0114  /*  Self Command Register */
#define PP_BusCTL               0x0116  /*  ISA bus control Register */
#define PP_TestCTL              0x0118  /*  Test Register */
#define PP_AutoNegCTL           0x011C  /*  Auto Negotiation Ctrl */

#define PP_ISQ                  0x0120  /*  Interrupt Status */
#define PP_RxEvent              0x0124  /*  Rx Event Register */
#define PP_TxEvent              0x0128  /*  Tx Event Register */
#define PP_BufEvent             0x012C  /*  Bus Event Register */
#define PP_RxMiss               0x0130  /*  Receive Miss Count */
#define PP_TxCol                0x0132  /*  Transmit Collision Count */
#define PP_LineST               0x0134  /*  Line State Register */
#define PP_SelfST               0x0136  /*  Self State register */
#define PP_BusST                0x0138  /*  Bus Status */
#define PP_TDR                  0x013C  /*  Time Domain Reflectometry */
#define PP_AutoNegST            0x013E  /*  Auto Neg Status */
#define PP_TxCommand            0x0144  /*  Tx Command */
#define PP_TxLength             0x0146  /*  Tx Length */
#define PP_LAF                  0x0150  /*  Hash Table */
#define PP_IA                   0x0158  /*  Physical Address Register */

#define PP_RxStatus             0x0400  /*  Receive start of frame */
#define PP_RxLength             0x0402  /*  Receive Length of frame */
#define PP_RxFrame              0x0404  /*  Receive frame pointer */
#define PP_TxFrame              0x0A00  /*  Transmit frame pointer */

/*  Primary I/O Base Address. If no I/O base is supplied by the user, then this */
/*  can be used as the default I/O base to access the PacketPage Area. */
#define DEFAULTIOBASE           0x0300
#define ADD_MASK                0x3000  /*  Mask it use of the ADD_PORT register */
#define ADD_SIG                 0x3000  /*  Expected ID signature */
#define EISA_ID_SIG             0x630E  /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */
#define PROD_ID_SIG             0x0900  /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */

/*  Defines Control/Config register quintuplet numbers */
#define RX_BUF_CFG              0x0003
#define RX_CONTROL              0x0005
#define TX_CFG                  0x0007
#define TX_COMMAND              0x0009
#define BUF_CFG                 0x000B
#define LINE_CONTROL            0x0013
#define SELF_CONTROL            0x0015
#define BUS_CONTROL             0x0017
#define TEST_CONTROL            0x0019

/*  Defines Status/Count registers quintuplet numbers */
#define RX_EVENT                0x0004
#define TX_EVENT                0x0008
#define BUF_EVENT               0x000C
#define RX_MISS_COUNT           0x0010
#define TX_COL_COUNT            0x0012
#define LINE_STATUS             0x0014
#define SELF_STATUS             0x0016
#define BUS_STATUS              0x0018
#define TDR                     0x001C

/* PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write */
#define SKIP_1 			0x0040
#define RX_STREAM_ENBL 		0x0080
#define RX_OK_ENBL 		0x0100
#define RX_DMA_ONLY 		0x0200
#define AUTO_RX_DMA 		0x0400
#define BUFFER_CRC 		0x0800
#define RX_CRC_ERROR_ENBL 	0x1000
#define RX_RUNT_ENBL 		0x2000
#define RX_EXTRA_DATA_ENBL 	0x4000

/* PP_RxCTL - Receive Control bit definition - Read/write */
#define RX_IA_HASH_ACCEPT 	0x0040
#define RX_PROM_ACCEPT 		0x0080
#define RX_OK_ACCEPT 		0x0100
#define RX_MULTCAST_ACCEPT 	0x0200
#define RX_IA_ACCEPT 		0x0400
#define RX_BROADCAST_ACCEPT 	0x0800
#define RX_BAD_CRC_ACCEPT 	0x1000
#define RX_RUNT_ACCEPT 		0x2000
#define RX_EXTRA_DATA_ACCEPT 	0x4000
#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
/*  Default receive mode - individually addressed, broadcast, and error free */
#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)

/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
#define TX_LOST_CRS_ENBL 	0x0040
#define TX_SQE_ERROR_ENBL 	0x0080
#define TX_OK_ENBL 		0x0100
#define TX_LATE_COL_ENBL 	0x0200
#define TX_JBR_ENBL 		0x0400
#define TX_ANY_COL_ENBL 	0x0800
#define TX_16_COL_ENBL 		0x8000

/* PP_TxCMD - Transmit Command bit definition - Read-only */
#define TX_START_4_BYTES 	0x0000
#define TX_START_64_BYTES 	0x0040
#define TX_START_128_BYTES 	0x0080
#define TX_START_ALL_BYTES 	0x00C0
#define TX_FORCE 		0x0100
#define TX_ONE_COL 		0x0200
#define TX_TWO_PART_DEFF_DISABLE 0x0400
#define TX_NO_CRC 		0x1000
#define TX_RUNT 		0x2000

/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
#define GENERATE_SW_INTERRUPT 	0x0040
#define RX_DMA_ENBL 		0x0080
#define READY_FOR_TX_ENBL 	0x0100
#define TX_UNDERRUN_ENBL 	0x0200
#define RX_MISS_ENBL 		0x0400
#define RX_128_BYTE_ENBL 	0x0800
#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
#define RX_DEST_MATCH_ENBL 	0x8000

/* PP_LineCTL - Line Control bit definition - Read/write */
#define SERIAL_RX_ON 		0x0040
#define SERIAL_TX_ON 		0x0080
#define AUI_ONLY 		0x0100
#define AUTO_AUI_10BASET 	0x0200
#define MODIFIED_BACKOFF 	0x0800
#define NO_AUTO_POLARITY 	0x1000
#define TWO_PART_DEFDIS 	0x2000
#define LOW_RX_SQUELCH 		0x4000

/* PP_SelfCTL - Software Self Control bit definition - Read/write */
#define POWER_ON_RESET 		0x0040
#define SW_STOP 		0x0100
#define SLEEP_ON 		0x0200
#define AUTO_WAKEUP 		0x0400
#define HCB0_ENBL 		0x1000
#define HCB1_ENBL 		0x2000
#define HCB0 			0x4000
#define HCB1 			0x8000

/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
#define RESET_RX_DMA 		0x0040
#define MEMORY_ON 		0x0400
#define DMA_BURST_MODE 		0x0800
#define IO_CHANNEL_READY_ON 	0x1000
#define RX_DMA_SIZE_64K 	0x2000
#define ENABLE_IRQ 		0x8000

/* PP_TestCTL - Test Control bit definition - Read/write */
#define LINK_OFF 		0x0080
#define ENDEC_LOOPBACK 		0x0200
#define AUI_LOOPBACK 		0x0400
#define BACKOFF_OFF 		0x0800
#define FAST_TEST 		0x8000

/* PP_RxEvent - Receive Event Bit definition - Read-only */
#define RX_IA_HASHED 		0x0040
#define RX_DRIBBLE 		0x0080
#define RX_OK 			0x0100
#define RX_HASHED 		0x0200
#define RX_IA 			0x0400
#define RX_BROADCAST 		0x0800
#define RX_CRC_ERROR 		0x1000
#define RX_RUNT 		0x2000
#define RX_EXTRA_DATA 		0x4000

#define HASH_INDEX_MASK 0x0FC00

/* PP_TxEvent - Transmit Event Bit definition - Read-only */
#define TX_LOST_CRS 		0x0040
#define TX_SQE_ERROR 		0x0080
#define TX_OK 			0x0100
#define TX_LATE_COL 		0x0200
#define TX_JBR 			0x0400
#define TX_16_COL 		0x8000
#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
#define TX_COL_COUNT_MASK 	0x7800

/* PP_BufEvent - Buffer Event Bit definition - Read-only */
#define SW_INTERRUPT 		0x0040
#define RX_DMA 			0x0080
#define READY_FOR_TX 		0x0100
#define TX_UNDERRUN 		0x0200
#define RX_MISS 		0x0400
#define RX_128_BYTE 		0x0800
#define TX_COL_OVRFLW 		0x1000
#define RX_MISS_OVRFLW 		0x2000
#define RX_DEST_MATCH 		0x8000

/* PP_SelfST - Chip Software Status bit definition */
#define ACTIVE_33V 		0x0040
#define INIT_DONE 		0x0080
#define SI_BUSY 		0x0100
#define EEPROM_PRESENT 		0x0200
#define EEPROM_OK 		0x0400
#define EL_PRESENT 		0x0800
#define EE_SIZE_64 		0x1000

/* PP_BusST - ISA Bus Status bit definition */
#define TX_BID_ERROR 		0x0080
#define READY_FOR_TX_NOW 	0x0100

/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
#define RE_NEG_NOW 		0x0040
#define ALLOW_FDX 		0x0080
#define AUTO_NEG_ENABLE 	0x0100
#define NLP_ENABLE 		0x0200
#define FORCE_FDX 		0x8000
#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)

/* PP_AutoNegST - Auto Negotiation Status bit definition */
#define AUTO_NEG_BUSY 		0x0080
#define FLP_LINK 		0x0100
#define FLP_LINK_GOOD 		0x0800
#define LINK_FAULT 		0x1000
#define HDX_ACTIVE 		0x4000
#define FDX_ACTIVE 		0x8000

/*  The following block defines the ISQ event types */
#define ISQ_RECEIVER_EVENT 	0x04
#define ISQ_TRANSMITTER_EVENT 	0x08
#define ISQ_BUFFER_EVENT 	0x0c
#define ISQ_RX_MISS_EVENT 	0x10
#define ISQ_TX_COL_EVENT 	0x12

#define ISQ_EVENT_MASK 		0x003F	/*  ISQ mask to find out type of event */
#define ISQ_HIST 		16	/*  small history buffer */
#define AUTOINCREMENT 		0x8000	/*  Bit mask to set bit-15 for autoincrement */

#define TXRXBUFSIZE 		0x0600
#define RXDMABUFSIZE 		0x8000
#define RXDMASIZE 		0x4000
#define TXRX_LENGTH_MASK 	0x07FF

/*  rx options bits */
#define RCV_WITH_RXON   1       /*  Set SerRx ON */
#define RCV_COUNTS      2       /*  Use Framecnt1 */
#define RCV_PONG        4       /*  Pong respondent */
#define RCV_DONG        8       /*  Dong operation */
#define RCV_POLLING     0x10    /*  Poll RxEvent */
#define RCV_ISQ         0x20    /*  Use ISQ, int */
#define RCV_AUTO_DMA    0x100   /*  Set AutoRxDMAE */
#define RCV_DMA         0x200   /*  Set RxDMA only */
#define RCV_DMA_ALL     0x400   /*  Copy all DMA'ed */
#define RCV_FIXED_DATA  0x800   /*  Every frame same */
#define RCV_IO          0x1000  /*  Use ISA IO only */
#define RCV_MEMORY      0x2000  /*  Use ISA Memory */

#define RAM_SIZE        0x1000       /*  The card has 4k bytes or RAM */
#define PKT_START PP_TxFrame  /*  Start of packet RAM */

#define RX_FRAME_PORT   0x0000
#define TX_FRAME_PORT RX_FRAME_PORT
#define TX_CMD_PORT     0x0004
#define TX_NOW          0x0000       /*  Tx packet after   5 bytes copied */
#define TX_AFTER_381    0x0040       /*  Tx packet after 381 bytes copied */
#define TX_AFTER_ALL    0x00c0       /*  Tx packet after all bytes copied */
#define TX_LEN_PORT     0x0006
#define ISQ_PORT        0x0008
#define ADD_PORT        0x000A
#define DATA_PORT       0x000C

/*  Receive Header */
/*  Description of header of each packet in receive area of memory */
#define RBUF_EVENT_LOW  0   /*  Low byte of RxEvent - status of received frame */
#define RBUF_EVENT_HIGH 1   /*  High byte of RxEvent - status of received frame */
#define RBUF_LEN_LOW    2   /*  Length of received data - low byte */
#define RBUF_LEN_HI     3   /*  Length of received data - high byte */
#define RBUF_HEAD_LEN   4   /*  Length of this header */

#define PACKET_PAGE_OFFSET 	0x8
#define STREAM_TRANSFER		0x2000

/*************************************************************
 *                                                           *
 *      CS8900A Ethernet MAC Function Proto types            *
 *                                                           *
 *************************************************************/