📄 config.lst
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C51 COMPILER V7.01 CONFIG 12/21/2004 12:24:41 PAGE 1
C51 COMPILER V7.01, COMPILATION OF MODULE CONFIG
OBJECT MODULE PLACED IN config.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE config.c BROWSE DEBUG OBJECTEXTEND
stmt level source
1 //---------------------------------------------------------------
2 // CYGNAL Integrated Products
3 //
4 // C Code Configuration Tool: F020 INITIALIZATION/CONFIGURATION CODE
5 //----------------------------------------------------------------
6 // This file is read only. To insert the code into your
7 // application, simply cut and paste or use the "Save As"
8 // command in the file menu to save the file in your project
9 // directory.
10 //----------------------------------------------------------------
11
12 //----------------------------------------------------------------
13 // INCLUDES
14 //----------------------------------------------------------------
15
16 #include <C8051F020.h> // Register definition file.
17
18 //------------------------------------------------------------------------------------
19 // Global CONSTANTS
20 //------------------------------------------------------------------------------------
21
22 //------------------------------------------------------------------------------------
23 // Function PROTOTYPES
24 //------------------------------------------------------------------------------------
25
26 //------------------------------------------------------------------------------------
27 // Config Routine
28 //------------------------------------------------------------------------------------
29 void config (void) {
30 1
31 1 //Local Variable Definitions
32 1 int n = 0;
33 1
34 1 EA = 0;
35 1
36 1 //----------------------------------------------------------------
37 1 // Watchdog Timer Configuration
38 1 //
39 1 // WDTCN.[7:0]: WDT Control
40 1 // Writing 0xA5 enables and reloads the WDT.
41 1 // Writing 0xDE followed within 4 clocks by 0xAD disables the WDT
42 1 // Writing 0xFF locks out disable feature.
43 1 //
44 1 // WDTCN.[2:0]: WDT timer interval bits
45 1 // NOTE! When writing interval bits, bit 7 must be a 0.
46 1 //
47 1 // Bit 2 | Bit 1 | Bit 0
48 1 //------------------------
49 1 // 1 | 1 | 1 Timeout interval = 1048576 x Tsysclk
50 1 // 1 | 1 | 0 Timeout interval = 262144 x Tsysclk
51 1 // 1 | 0 | 1 Timeout interval = 65636 x Tsysclk
52 1 // 1 | 0 | 0 Timeout interval = 16384 x Tsysclk
53 1 // 0 | 1 | 1 Timeout interval = 4096 x Tsysclk
54 1 // 0 | 1 | 0 Timeout interval = 1024 x Tsysclk
55 1 // 0 | 0 | 1 Timeout interval = 256 x Tsysclk
C51 COMPILER V7.01 CONFIG 12/21/2004 12:24:41 PAGE 2
56 1 // 0 | 0 | 0 Timeout interval = 64 x Tsysclk
57 1 //
58 1 //------------------------
59 1
60 1 WDTCN = 0x07; // Watchdog Timer Control Register
61 1 WDTCN = 0xDE; // Disable WDT
62 1 WDTCN = 0xAD;
63 1
64 1 //----------------------------------------------------------------
65 1 // CROSSBAR REGISTER CONFIGURATION
66 1 //
67 1 // NOTE: The crossbar register should be configured before any
68 1 // of the digital peripherals are enabled. The pinout of the
69 1 // device is dependent on the crossbar configuration so caution
70 1 // must be exercised when modifying the contents of the XBR0,
71 1 // XBR1, and XBR2 registers. For detailed information on
72 1 // Crossbar Decoder Configuration, refer to Application Note
73 1 // AN001, "Configuring the Port I/O Crossbar Decoder".
74 1 //----------------------------------------------------------------
75 1
76 1 // Configure the XBRn Registers
77 1
78 1 XBR0 = 0x04; // 使用UART0
79 1 XBR1 = 0x14; // 使用INT0,INT1
80 1 XBR2 = 0x44; // 允许交叉开关，同时使用UART1的管脚
81 1 // Select Pin I/0
82 1
83 1 // NOTE: Some peripheral I/O pins can function as either inputs or
84 1 // outputs, depending on the configuration of the peripheral. By default,
85 1 // the configuration utility will configure these I/O pins as push-pull
86 1 // outputs.
87 1 // Port configuration (1 = Push Pull Output)
88 1 P0MDOUT = 0x00; // Output configuration for P0
89 1 P1MDOUT = 0x00; // Output configuration for P1
90 1 P2MDOUT = 0x00; // Output configuration for P2
91 1 P3MDOUT = 0x00; // Output configuration for P3
92 1 P74OUT = 0xFF; // Output configuration for P4-7
93 1
94 1 P1MDIN = 0xFF; // 数字输入方式
95 1
96 1 // View port pinout
97 1
98 1 // The current Crossbar configuration results in the
99 1 // following port pinout assignment:
100 1 // Port 0
101 1 // P0.0 = UART TX0 (Open-Drain Output/Input)
102 1 // P0.1 = UART RX0 (Open-Drain Output/Input)
103 1 // P0.2 = T0 (Open-Drain Output/Input)
104 1 // P0.3 = /INT0 (Open-Drain Output/Input)
105 1 // P0.4 = GP I/O (Open-Drain Output/Input)
106 1 // P0.5 = Skipped (Open-Drain Output/Input)(Analog)
107 1 // P0.6 = Skipped (Open-Drain Output/Input)(Analog)
108 1 // P0.7 = Skipped (Open-Drain Output/Input)(Analog)
109 1
110 1 // Port 1
111 1 // P1.0 = GP I/O (Open-Drain Output/Input)(Digital)
112 1 // P1.1 = GP I/O (Open-Drain Output/Input)(Digital)
113 1 // P1.2 = GP I/O (Open-Drain Output/Input)(Digital)
114 1 // P1.3 = GP I/O (Open-Drain Output/Input)(Digital)
115 1 // P1.4 = GP I/O (Open-Drain Output/Input)(Digital)
116 1 // P1.5 = GP I/O (Open-Drain Output/Input)(Digital)
117 1 // P1.6 = GP I/O (Open-Drain Output/Input)(Digital)
C51 COMPILER V7.01 CONFIG 12/21/2004 12:24:41 PAGE 3
118 1 // P1.7 = GP I/O (Open-Drain Output/Input)(Digital)
119 1
120 1 // Port 2
121 1 // P2.0 = GP I/O (Open-Drain Output/Input)
122 1 // P2.1 = GP I/O (Open-Drain Output/Input)
123 1 // P2.2 = GP I/O (Open-Drain Output/Input)
124 1 // P2.3 = GP I/O (Open-Drain Output/Input)
125 1 // P2.4 = GP I/O (Open-Drain Output/Input)
126 1 // P2.5 = GP I/O (Open-Drain Output/Input)
127 1 // P2.6 = GP I/O (Open-Drain Output/Input)
128 1 // P2.7 = GP I/O (Open-Drain Output/Input)
129 1
130 1 // Port 3
131 1 // P3.0 = GP I/O (Open-Drain Output/Input)
132 1 // P3.1 = GP I/O (Open-Drain Output/Input)
133 1 // P3.2 = GP I/O (Open-Drain Output/Input)
134 1 // P3.3 = GP I/O (Open-Drain Output/Input)
135 1 // P3.4 = GP I/O (Open-Drain Output/Input)
136 1 // P3.5 = GP I/O (Open-Drain Output/Input)
137 1 // P3.6 = GP I/O (Open-Drain Output/Input)
138 1 // P3.7 = GP I/O (Open-Drain Output/Input)
139 1
140 1 EMI0CF = 0x34; //外部存储接口在高端口，非复用方式
141 1
142 1 //----------------------------------------------------------------
143 1 // Comparators Register Configuration
144 1 //
145 1 // Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
146 1 //------------------------------------------------------------------
147 1 // R/W | R | R/W | R/W | R/W | R/W | R/W | R/W
148 1 //------------------------------------------------------------------
149 1 // Enable | Output | Rising | Falling| Positive | Negative
150 1 // | State | Edge | Edge | Hysterisis | Hysterisis
151 1 // | Flag | Int. | Int. | 00: Disable | 00: Disable
152 1 // | | Flag | Flag | 01: 5mV | 01: 5mV
153 1 // | | | | 10: 10mV | 10: 10mV
154 1 // | | | | 11: 20mV | 11: 20mV
155 1 // ----------------------------------------------------------------
156 1
157 1 CPT0CN = 0x00; // Comparator 0 Control Register
158 1
159 1
160 1 CPT1CN = 0x00; // Comparator 1 Control Register
161 1
162 1 //Comp1 marker
163 1
164 1 //----------------------------------------------------------------
165 1 // Oscillator Configuration
166 1 //----------------------------------------------------------------
167 1
168 1 OSCXCN = 0x67; // EXTERNAL Oscillator Control Register
169 1 for (n = 0; n < 255; n++) ; // wait for osc to start
170 1 while ( (OSCXCN & 0x80) == 0 ); // wait for xtal to stabilize
171 1
172 1 OSCICN = 0x08; // Internal Oscillator Control Register
173 1
174 1
175 1 //----------------------------------------------------------------
176 1 // Reference Control Register Configuration
177 1 //----------------------------------------------------------------
178 1
179 1 REF0CN = 0x00; // Reference Control Register
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