io.h

M*core开发库文件,能够大大减轻开发者的难度

/********************************************************************
	created:	2007/04/13
	created:	13:4:2007   11:26
	filename: 	G:\DataBak\VCWorks\04.09\McoreReg\IO.h
	author:		CryinRain & YxY
	Page:       72<->78
	purpose:	I/O port module regs,!! just at the no_simulater state.
*********************************************************************/
#if !defined(_CORE_H7)
#define _CORE_H7

//Port output data regs
#define PORTA	(*(volatile unsigned char*)(0x00c00000))	//8bit Access:S/U		R/W
#define PORTB	(*(volatile unsigned char*)(0x00c00001))	//8bit Access:S/U		R/W
#define PORTC	(*(volatile unsigned char*)(0x00c00002))	//8bit Access:S/U		R/W
#define PORTD	(*(volatile unsigned char*)(0x00c00003))	//8bit Access:S/U		R/W
#define PORTE	(*(volatile unsigned char*)(0x00c00004))	//8bit Access:S/U		R/W
#define PORTF	(*(volatile unsigned char*)(0x00c00005))	//8bit Access:S/U		R/W
#define PORTG	(*(volatile unsigned char*)(0x00c00006))	//8bit Access:S/U		R/W
#define PORTH	(*(volatile unsigned char*)(0x00c00007))	//8bit Access:S/U		R/W
#define PORTI	(*(volatile unsigned char*)(0x00c00008))	//8bit Access:S/U		R/W

//Port data transfer direction
#define DDRA	(*(volatile unsigned char*)(0x00c0000c))	//8bit Access:S/U		R/W 
#define DDRB	(*(volatile unsigned char*)(0x00c0000d))	//8bit Access:S/U		R/W 
#define DDRC	(*(volatile unsigned char*)(0x00c0000e))	//8bit Access:S/U		R/W 
#define DDRD	(*(volatile unsigned char*)(0x00c0000f))	//8bit Access:S/U		R/W 
#define DDRE	(*(volatile unsigned char*)(0x00c00010))	//8bit Access:S/U		R/W 
#define DDRF	(*(volatile unsigned char*)(0x00c00011))	//8bit Access:S/U		R/W 
#define DDRG	(*(volatile unsigned char*)(0x00c00012))	//8bit Access:S/U		R/W 
#define DDRH	(*(volatile unsigned char*)(0x00c00013))	//8bit Access:S/U		R/W 
#define DDRI	(*(volatile unsigned char*)(0x00c00014))	//8bit Access:S/U		R/W 


//! the PORTAP and SETA at the same Reg_Address.
//Port leads state	(Yinjiao data reg)
#define PORTAP	(*(volatile unsigned char*)(0x00c00018))	//8bit Access:S/U		R :just return the leads state now!
#define PORTBP	(*(volatile unsigned char*)(0x00c00019))	//8bit Access:S/U		R
#define PORTCP	(*(volatile unsigned char*)(0x00c0001a))	//8bit Access:S/U		R
#define PORTDP	(*(volatile unsigned char*)(0x00c0001b))	//8bit Access:S/U		R
#define PORTEP	(*(volatile unsigned char*)(0x00c0001c))	//8bit Access:S/U		R
#define PORTFP	(*(volatile unsigned char*)(0x00c0001d))	//8bit Access:S/U		R
#define PORTGP	(*(volatile unsigned char*)(0x00c0001e))	//8bit Access:S/U		R
#define PORTHP	(*(volatile unsigned char*)(0x00c0001f))	//8bit Access:S/U		R
#define PORTIP	(*(volatile unsigned char*)(0x00c00020))	//8bit Access:S/U		R

//Port Set leads state, set 1 at SETX will set the corresponding bit of the PortX
#define SETA	(*(volatile unsigned char*)(0x00c00018))	//8bit Access:S/U		W :just set 1,set 0 invalidate
#define SETB	(*(volatile unsigned char*)(0x00c00019))	//8bit Access:S/U		W
#define SETC	(*(volatile unsigned char*)(0x00c0001a))	//8bit Access:S/U		W
#define SETD	(*(volatile unsigned char*)(0x00c0001b))	//8bit Access:S/U		W
#define SETE	(*(volatile unsigned char*)(0x00c0001c))	//8bit Access:S/U		W
#define SETF	(*(volatile unsigned char*)(0x00c0001d))	//8bit Access:S/U		W
#define SETG	(*(volatile unsigned char*)(0x00c0001e))	//8bit Access:S/U		W
#define SETH	(*(volatile unsigned char*)(0x00c0001f))	//8bit Access:S/U		W
#define SETI	(*(volatile unsigned char*)(0x00c00020))	//8bit Access:S/U		W

//Clear Port output' data
#define CLRA	(*(volatile unsigned char*)(0x00c00024))	//8bit Access:S/U		R/W :set 0 clr, set 1 invalidate
#define CLRB	(*(volatile unsigned char*)(0x00c00025))	//8bit Access:S/U		R/W 
#define CLRC	(*(volatile unsigned char*)(0x00c00026))	//8bit Access:S/U		R/W
#define CLRD	(*(volatile unsigned char*)(0x00c00027))	//8bit Access:S/U		R/W 
#define CLRE	(*(volatile unsigned char*)(0x00c00028))	//8bit Access:S/U		R/W 
#define CLRF	(*(volatile unsigned char*)(0x00c00029))	//8bit Access:S/U		R/W 
#define CLRG	(*(volatile unsigned char*)(0x00c0002a))	//8bit Access:S/U		R/W 
#define CLRH	(*(volatile unsigned char*)(0x00c0002b))	//8bit Access:S/U		R/W 
#define CLRI	(*(volatile unsigned char*)(0x00c0002c))	//8bit Access:S/U		R/W 

//Port C/D leads distribute
#define PCDPAR	(*(volatile unsigned char*)(0x00c00030))	//8bit Access:S/U		R/W 
//:Set for choose 32/16Bit exterior BUS

#define PEDPAR	(*(volatile unsigned char*)(0x00c00031))	//8bit Access:S/U		R/W 
//:Set for choose PortE leads original fuc or I/O




//////////////////////////////////////////////////////////////////////////
//Edge Port Module regs
#define EPPAR	(*(volatile unsigned short*)(0x00c60000))	//16bit Access:S		R/W
#define EPDDR	(*(volatile unsigned char*)(0x00c60002))	//8bit	Access:S		R/W
#define EPIER	(*(volatile unsigned char*)(0x00c60003))	//8bit	Access:S		R/W
#define EPDR	(*(volatile unsigned char*)(0x00c60004))	//8bit	Access:S		R/W
#define EPPDR	(*(volatile unsigned char*)(0x00c60005))	//8bit	Access:S/U		R
#define EPFR	(*(volatile unsigned char*)(0x00c60006))	//8bit	Access:S/U		R	 !:but Set 1 for CLR

#endif