📄 interrupt.h
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/********************************************************************
created: 2007/04/13
created: 13:4:2007 10:53
filename: G:\DataBak\VCWorks\04.09\McoreReg\Interrupt.h
author: CryinRain & YxY
Page: 63<->67
purpose: Interrupt control module
*********************************************************************/
#if !defined(_CORE_H6)
#define _CORE_H6
//#include "InterruptSupport.s"
extern void Write_PSR(unsigned long);
extern unsigned long Read_PSR(void);
#define ICR (*(volatile unsigned short*)(0x00c50000)) //16bit Access:S/U R/W Interrupt control reg
#define ISR (*(volatile unsigned short*)(0x00c50002)) //16bit Access:S/U R Interrupt state reg
#define IFRH (*(volatile unsigned long*)(0x00c50004)) //32bit Access:S/U R/W IFRH: force interrupt
#define IFRL (*(volatile unsigned long*)(0x00c50008)) //32bit Access:S/U R/W IFRL: force interrupt
//PLS[4:0] From 1-->32,32 has the highest PRI,0 is the lowest.
#define PLSR0 (*(volatile unsigned char*)(0x00c50040)) //8bit Access:S R/W QADC: PF1
#define PLSR1 (*(volatile unsigned char*)(0x00c50041)) //8bit Access:S R/W CF1
#define PLSR2 (*(volatile unsigned char*)(0x00c50042)) //8bit Access:S R/W PF2
#define PLSR3 (*(volatile unsigned char*)(0x00c50043)) //8bit Access:S R/W CF2
#define PLSR4 (*(volatile unsigned char*)(0x00c50044)) //8bit Access:S R/W SPI: MODF
#define PLSR5 (*(volatile unsigned char*)(0x00c50045)) //8bit Access:S R/W SPIF
#define PLSR6 (*(volatile unsigned char*)(0x00c50046)) //8bit Access:S R/W SCI1: TDRE
#define PLSR7 (*(volatile unsigned char*)(0x00c50047)) //8bit Access:S R/W TC
#define PLSR8 (*(volatile unsigned char*)(0x00c50048)) //8bit Access:S R/W RDRF
#define PLSR9 (*(volatile unsigned char*)(0x00c50049)) //8bit Access:S R/W OR
#define PLSR10 (*(volatile unsigned char*)(0x00c5004A)) //8bit Access:S R/W IDLE
#define PLSR11 (*(volatile unsigned char*)(0x00c5004B)) //8bit Access:S R/W SCI2: TDRE
#define PLSR12 (*(volatile unsigned char*)(0x00c5004C)) //8bit Access:S R/W TC
#define PLSR13 (*(volatile unsigned char*)(0x00c5004D)) //8bit Access:S R/W RDRF
#define PLSR14 (*(volatile unsigned char*)(0x00c5004E)) //8bit Access:S R/W OR
#define PLSR15 (*(volatile unsigned char*)(0x00c5004F)) //8bit Access:S R/W IDLE
#define PLSR16 (*(volatile unsigned char*)(0x00c50050)) //8bit Access:S R/W TIM1: C0F
#define PLSR17 (*(volatile unsigned char*)(0x00c50051)) //8bit Access:S R/W C1F
#define PLSR18 (*(volatile unsigned char*)(0x00c50052)) //8bit Access:S R/W C2F
#define PLSR19 (*(volatile unsigned char*)(0x00c50053)) //8bit Access:S R/W C3F
#define PLSR20 (*(volatile unsigned char*)(0x00c50054)) //8bit Access:S R/W TOF
#define PLSR21 (*(volatile unsigned char*)(0x00c50055)) //8bit Access:S R/W PAIF
#define PLSR22 (*(volatile unsigned char*)(0x00c50056)) //8bit Access:S R/W PAOVF
#define PLSR23 (*(volatile unsigned char*)(0x00c50057)) //8bit Access:S R/W TIM2: C0F
#define PLSR24 (*(volatile unsigned char*)(0x00c50058)) //8bit Access:S R/W C1F
#define PLSR25 (*(volatile unsigned char*)(0x00c50059)) //8bit Access:S R/W C2F
#define PLSR26 (*(volatile unsigned char*)(0x00c5005A)) //8bit Access:S R/W C3F
#define PLSR27 (*(volatile unsigned char*)(0x00c5005B)) //8bit Access:S R/W TOF
#define PLSR28 (*(volatile unsigned char*)(0x00c5005C)) //8bit Access:S R/W PAIF
#define PLSR29 (*(volatile unsigned char*)(0x00c5005D)) //8bit Access:S R/W PAOVF
#define PLSR30 (*(volatile unsigned char*)(0x00c5005E)) //8bit Access:S R/W PIT1
#define PLSR31 (*(volatile unsigned char*)(0x00c5005F)) //8bit Access:S R/W PIT2
#define PLSR32 (*(volatile unsigned char*)(0x00c50060)) //8bit Access:S R/W EPORT: EPF0
#define PLSR33 (*(volatile unsigned char*)(0x00c50061)) //8bit Access:S R/W EPF1
#define PLSR34 (*(volatile unsigned char*)(0x00c50062)) //8bit Access:S R/W EPF2
#define PLSR35 (*(volatile unsigned char*)(0x00c50063)) //8bit Access:S R/W EPF3
#define PLSR36 (*(volatile unsigned char*)(0x00c50064)) //8bit Access:S R/W EPF4
#define PLSR37 (*(volatile unsigned char*)(0x00c50065)) //8bit Access:S R/W EPF5
#define PLSR38 (*(volatile unsigned char*)(0x00c50066)) //8bit Access:S R/W EPF6
#define PLSR39 (*(volatile unsigned char*)(0x00c50067)) //8bit Access:S R/W EPF7
#define IPR (*(volatile unsigned long*)(0x00c5000c)) //32bit Access:S/U R Interrupt pause reg
#define NIER (*(volatile unsigned long*)(0x00c50010)) //32bit Access:S/U R/W Normal interrupt enable reg
#define NIPR (*(volatile unsigned long*)(0x00c50014)) //32bit Access:S/U R Normal interrupt Pause reg
#define FIER (*(volatile unsigned long*)(0x00c50018)) //32bit Access:S/U R/W Fast interrupt enable reg
#define FIPR (*(volatile unsigned long*)(0x00c5001C)) //32bit Access:S/U R Fast interrupt enable reg
//////////////////////////////////////////////////////////////////////////
/*Interrupt control macro define*/
#define MMC2107OnChipSram 0x00800000 //interior SRAM start address
#define ExternMem 0x810E0000 //exterior RAM start address
#define EnableInterrupt Write_PSR(Read_PSR() | EE | IE | FE) //enable int
#define DisableInterrupt Write_PSR(Read_PSR() & ~EE & ~IE & ~FE) //disable int
#define InstallVector(isr,address) (*(void**)(address)=(isr))
#define InstallAltVector(isr,address) (*(void**)(address)=(void*)((unsigned long)(isr)+1))
/*Interrupt information*/
#define AllowAutoVectors 0x8000 //set autovector interrupt
#define AllowVectors 0x0000 //set vector interrupt
//////////////////////////////////////////////////////////////////////////
//
#define PriorityLevel0 0x00
#define PriorityLevel1 0x01
#define PriorityLevel2 0x02
#define PriorityLevel3 0x03
#define PriorityLevel4 0x04
#define PriorityLevel5 0x05
#define PriorityLevel6 0x06
#define PriorityLevel7 0x07
#define PriorityLevel8 0x08
#define PriorityLevel9 0x09
#define PriorityLevel10 0x0A
#define PriorityLevel11 0x0B
#define PriorityLevel12 0x0C
#define PriorityLevel13 0x0D
#define PriorityLevel14 0x0E
#define PriorityLevel15 0x0F
#define PriorityLevel16 0x10
#define PriorityLevel17 0x11
#define PriorityLevel18 0x12
#define PriorityLevel19 0x13
#define PriorityLevel20 0x14
#define PriorityLevel21 0x15
#define PriorityLevel22 0x16
#define PriorityLevel23 0x17
#define PriorityLevel24 0x18
#define PriorityLevel25 0x19
#define PriorityLevel26 0x1A
#define PriorityLevel27 0x1B
#define PriorityLevel28 0x1C
#define PriorityLevel29 0x1D
#define PriorityLevel30 0x1E
#define PriorityLevel31 0x1F
//////////////////////////////////////////////////////////////////////////
//enable priorityLevelEnx
#define PriorityLevelEn0 0x00000001
#define PriorityLevelEn1 0x00000002
#define PriorityLevelEn2 0x00000004
#define PriorityLevelEn3 0x00000008
#define PriorityLevelEn4 0x00000010
#define PriorityLevelEn5 0x00000020
#define PriorityLevelEn6 0x00000040
#define PriorityLevelEn7 0x00000080
#define PriorityLevelEn8 0x00000100
#define PriorityLevelEn9 0x00000200
#define PriorityLevelEn10 0x00000400
#define PriorityLevelEn11 0x00000800
#define PriorityLevelEn12 0x00001000
#define PriorityLevelEn13 0x00002000
#define PriorityLevelEn14 0x00004000
#define PriorityLevelEn15 0x00008000
#define PriorityLevelEn16 0x00010000
#define PriorityLevelEn17 0x00020000
#define PriorityLevelEn18 0x00040000
#define PriorityLevelEn19 0x00080000
#define PriorityLevelEn20 0x00100000
#define PriorityLevelEn21 0x00200000
#define PriorityLevelEn22 0x00400000
#define PriorityLevelEn23 0x00800000
#define PriorityLevelEn24 0x01000000
#define PriorityLevelEn25 0x02000000
#define PriorityLevelEn26 0x04000000
#define PriorityLevelEn27 0x08000000
#define PriorityLevelEn28 0x10000000
#define PriorityLevelEn29 0x20000000
#define PriorityLevelEn30 0x40000000
#define PriorityLevelEn31 0x80000000
#define VectorOffset 32 //abnormal interrupt stand in 0--31 vector num
/*=============================================================*/
/* Bit positions and macros common to both boards */
/*=============================================================*/
/* Bit names for general use */
#define bit31 0x80000000
#define bit30 0x40000000
#define bit29 0x20000000
#define bit28 0x10000000
#define bit27 0x08000000
#define bit26 0x04000000
#define bit25 0x02000000
#define bit24 0x01000000
#define bit23 0x00800000
#define bit22 0x00400000
#define bit21 0x00200000
#define bit20 0x00100000
#define bit19 0x00080000
#define bit18 0x00040000
#define bit17 0x00020000
#define bit16 0x00010000
#define bit15 0x00008000
#define bit14 0x00004000
#define bit13 0x00002000
#define bit12 0x00001000
#define bit11 0x00000800
#define bit10 0x00000400
#define bit09 0x00000200
#define bit08 0x00000100
#define bit07 0x00000080
#define bit06 0x00000040
#define bit05 0x00000020
#define bit04 0x00000010
#define bit03 0x00000008
#define bit02 0x00000004
#define bit01 0x00000002
#define bit00 0x00000001
/* Processor Status Register (PSR) bits */
#define PSR_S bit31 /* Supervisor/user mode. 1 = supervisor */
#define PSR_SP bit29+bit28 /* Spare bits - write 0 */
#define U3 bit27 /* Hardware Accelerator Control bits */
#define U2 bit26
#define U1 bit25
#define U0 bit24
/* Vector number */
#define PSR_VEC bit22+bit21+bit20+bit19+bit18+bit17+bit16
#define TM bit15+bit14 /* Trace mode bits */
#define TP bit13 /* Trace pending */
#define TCTL bit12 /* Translation control bit for external mem */
#define SC bit10 /* Spare Control */
#define MM bit09 /* Misalignment Exception Mask */
#define EE bit08 /* Exception Enable */
#define IC bit07 /* Interrupt Control */
#define IE bit06 /* Interrupt Enable */
#define FE bit04 /* Fast Interrupt Enable */
#define AF bit01 /* Alternate File Enable */
#define C bit00 /* Condition Control/Carry bit */
/* Macros and functions for controlling interrupts */
#endif⌨️ 快捷键说明
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