or4x32_reg.vhd

VHDL设计实例

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;


entity OR4X32_REG is
    port (
        BUSA: in STD_LOGIC_VECTOR (31 downto 0);
        BUSB: in STD_LOGIC_VECTOR (31 downto 0);
        BUSC: in STD_LOGIC_VECTOR (31 downto 0);
        BUSD: in STD_LOGIC_VECTOR (31 downto 0);
        CLK: in STD_LOGIC;
        DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0)
    );
end OR4X32_REG;

architecture OR4X32_REG_arch of OR4X32_REG is

signal OR_BUS: STD_LOGIC_VECTOR (31 downto 0);

begin

process(BUSA,BUSB,BUSC,BUSD)

variable TEMP : STD_LOGIC_VECTOR (31 downto 0); 

begin
    for I in 0 to 31 loop
        TEMP(I) := BUSA(I) or BUSB(I) or BUSC(I) or BUSD(I);
    end loop;
    OR_BUS <= TEMP;
end process;

process(CLK)
begin
    if (CLK'event and CLK = '1') then
        DATA_OUT <= OR_BUS;
    end if;
end process;

end OR4X32_REG_arch;