wr_cntrl.vhd

VHDL设计实例

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;

--
-- Write Control Logic - Consists of eight 3-bit, that count synchronously, with the counter
-- that drives WADDR_A initializes to 0 at reset, WADDR_B initializes to 7, C to 6, etc. It also
-- contains a 32-bit one-hot state-machine, which is just a 32 bit shift register, that initializes
-- to FE000001 on reset.
--


entity WR_CNTRL is
    port (
	DP_WR_EN : out STD_LOGIC_VECTOR (31 downto 0);
	WA_MSB : out STD_LOGIC_VECTOR (3 downto 0);
	WRITE_ADDRESS : out WRITE_ADDRESS_ARRAY;
	CLK : in STD_LOGIC;
	RESET : in STD_LOGIC;
	INCREMENT_BCOUNT: out STD_LOGIC;
	WRITE_ENABLE : in STD_LOGIC
    );
end WR_CNTRL;

architecture WR_CNTRL_arch of WR_CNTRL is
--
-- Internal versions of output vectors
--
signal WRITE_ADDRESS_INT: WRITE_ADDRESS_ARRAY;
signal DP_WR_EN_INT: STD_LOGIC_VECTOR (31 downto 0);
signal WA_MSB_INT: STD_LOGIC_VECTOR(3 downto 0);
signal BIT_COUNT: INTEGER range 0 to 31;

begin
--
-- Assign signals to outputs
--
WRITE_ADDRESS <= WRITE_ADDRESS_INT;
DP_WR_EN <= DP_WR_EN_INT;
WA_MSB <= WA_MSB_INT;
--
-- Count number of bits written to a 32 bit word 
--
process (CLK, RESET)
begin
   if RESET='1' then
      BIT_COUNT <= 0;
      INCREMENT_BCOUNT <= '0';
   elsif CLK='1' and CLK'event then
	if WRITE_ENABLE ='1' then
	    BIT_COUNT <= BIT_COUNT + 1;
	    if BIT_COUNT = 30 then
		INCREMENT_BCOUNT <= '1';
            else
		INCREMENT_BCOUNT <= '0';
            end if;
        end if;
   end if;
end process;
--
--  Create eight 3-bit counters, that are the control inputs to the 8x1 muxes
--  and are also the address to the dual-port RAMS -  INITIALIZE TO 0(8),7,6,5,4,3,2,1
--
-- INITIALIZE TO 7,6,5,4,3,2,1,0
--
process (CLK, RESET)
variable TEMP:STD_LOGIC_VECTOR(4 downto 0);
begin
       if RESET='1' then
--           for I in 0 to 7 loop
--               TEMP := CONV_STD_LOGIC_VECTOR((8-I),5);
--               WRITE_ADDRESS_INT(I) <= TEMP(2 downto 0);
--           end loop;
           for I in 0 to 7 loop
               TEMP := CONV_STD_LOGIC_VECTOR((7-I),5);
               WRITE_ADDRESS_INT(I) <= TEMP(2 downto 0);
           end loop;
       elsif CLK='1' and CLK'event then
           if WRITE_ENABLE='1' then
               for I in 0 to 7 loop
               WRITE_ADDRESS_INT(I) <= WRITE_ADDRESS_INT(I)+1;
           end loop;
           end if;
       end if;
end process;
--
-- State machine to create the write enables to the thirty-two 16x1 dual-port RAMS
--
process(CLK,RESET)
begin
    if RESET = '1' then
--        DP_WR_EN_INT <= "11111110000000000000000000000001";
        DP_WR_EN_INT <= "11111111000000000000000000000000";
    elsif CLK'event and CLK = '1' then
        if WRITE_ENABLE = '1' then
            DP_WR_EN_INT <= DP_WR_EN_INT(30 downto 0) & DP_WR_EN_INT(31);
        end if;
    end if;
end process;
--
-- Control of the MSB of write address
--
process(CLK, RESET)
begin
    if RESET = '1' then
        WA_MSB_INT <= "1000";
    elsif CLK'event and CLK = '1' then
        if WRITE_ENABLE = '1' then
            if (DP_WR_EN_INT(8) = '1' and DP_WR_EN_INT(7) = '0') then
                WA_MSB_INT(0) <= not(WA_MSB_INT(0));
            end if;
            if (DP_WR_EN_INT(16) = '1' and DP_WR_EN_INT(15) = '0') then
                WA_MSB_INT(1) <= not(WA_MSB_INT(1));
            end if;
            if (DP_WR_EN_INT(24) = '1' and DP_WR_EN_INT(23) = '0') then
                WA_MSB_INT(2) <= not(WA_MSB_INT(2));
            end if;
            if (DP_WR_EN_INT(0) = '1' and DP_WR_EN_INT(31) = '0') then
                WA_MSB_INT(3) <= not(WA_MSB_INT(3));
            end if;
        end if;
    end if;
end process;

end WR_CNTRL_arch;