reg32.vhd

VHDL设计实例

--
--  Thirty-two bit register
--
library IEEE;
use IEEE.std_logic_1164.all;

entity REG32 is
    port (
        CLK: in STD_LOGIC;
        D: in STD_LOGIC_VECTOR (31 downto 0);
        Q: out STD_LOGIC_VECTOR (31 downto 0)
    );
end REG32;

architecture REG32_arch of REG32 is
begin

process (CLK)
begin
   if CLK'event and CLK='1' then  --CLK rising edge
      Q <= D;
   end if;
end process;

end REG32_arch;