delay.vhd

VHDL设计实例

--
-- This module causes the input signal to be delayed DELAY_LENGTH clock cycles.
-- The delays are implemented using SHIFT REGISTER LUTS.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;


entity DELAY is
    generic(DELAY_LENGTH: INTEGER);
    port (
	CLK: in STD_LOGIC;
	CE: in STD_LOGIC;
	DIN: in STD_LOGIC;
	DOUT: out STD_LOGIC
    );
end DELAY;

architecture DELAY_arch of DELAY is

component SRL16E
   port (D: in STD_LOGIC;
       CE: in STD_LOGIC;
       CLK: in STD_LOGIC;
       A0: in STD_LOGIC;
       A1: in STD_LOGIC;
       A2: in STD_LOGIC;
       A3: in STD_LOGIC;
       Q: out STD_LOGIC
       ) ;
end component ;

signal TEMP: STD_LOGIC_VECTOR(3 downto 0);

begin

--TEMP <= (CONV_STD_LOGIC_VECTOR(DELAY_LENGTH,4)-1);
TEMP <= CONV_STD_LOGIC_VECTOR(DELAY_LENGTH,4);
--
-- If the delay is zero, don't use the SRLUT, and just pass the data through
--
--DELAY0:
--if DELAY_LENGTH = 0 generate
--   DOUT <= DIN;
--end generate;
--
-- If the delay is not zero, use the SRLUT to cause the delay
-- 
--DELAY1:
--if DELAY_LENGTH /= 0 generate
SRL1: SRL16E
   port map (
       D=> DIN,
       CE=> CE,
       CLK=> CLK,
       A0=> TEMP(0),
       A1=> TEMP(1),
       A2=> TEMP(2),
       A3=> TEMP(3),
       Q=> DOUT
    );
--end generate;

end DELAY_arch;