output_pipeline.vhd

VHDL设计实例

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;



library WORK1;
use WORK1.SER_PAR_LIB.all;

entity OUTPUT_PIPELINE is
    generic(
        NUMBER_OF_BANKS: INTEGER;
        NUMBER_OF_STAGES: INTEGER
        );
    port (
        DATA_IN:in DATA_OUT_ARRAY;
        RD_CLK: in STD_LOGIC;
        READ_ENABLE: in STD_LOGIC;
        READ_ENABLE_OUT: out STD_LOGIC;
        DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0)
    );
end OUTPUT_PIPELINE;

architecture OUTPUT_PIPELINE_arch of OUTPUT_PIPELINE is

component OR4X32_REG
    port (
        BUSA: in STD_LOGIC_VECTOR (31 downto 0);
        BUSB: in STD_LOGIC_VECTOR (31 downto 0);
        BUSC: in STD_LOGIC_VECTOR (31 downto 0);
        BUSD: in STD_LOGIC_VECTOR (31 downto 0);
        CLK: in STD_LOGIC;
        DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0)
    );
end component;

component DELAY
    generic(DELAY_LENGTH: INTEGER);
    port (
	CLK: in STD_LOGIC;
	CE: in STD_LOGIC;
	DIN: in STD_LOGIC;
	DOUT: out STD_LOGIC
    );
end component ;

constant ZERO_32: STD_LOGIC_VECTOR := "00000000000000000000000000000000";

signal BANK_DATA: DATA_OUT_ARRAY;

--constant DELAY_LENGTH: INTEGER:= stages + 3;
signal TEMP: INTEGER;

type TEMP_ARRAY is array (0 to 19) of STD_LOGIC_VECTOR (31 downto 0);
signal TEMP_ARRAY_DATA: TEMP_ARRAY;

signal VCC: STD_LOGIC;

begin
VCC <= '1';

GEN0:for I in 0 to NUMBER_OF_BANKS-1 generate
        BANK_DATA(I) <= DATA_IN(I);
    end generate;
    
GEN1:if (NUMBER_OF_BANKS /= 63) generate
        GEN2:for I in NUMBER_OF_BANKS to 63 generate
            BANK_DATA(I) <=  ZERO_32;
        end generate;
    end generate;

stage0:
if stages=0 generate
    OR0:OR4X32_REG
        port map (
            BUSA => BANK_DATA(0),
            BUSB => BANK_DATA(1),
            BUSC => BANK_DATA(2),
            BUSD => BANK_DATA(3),
            CLK => RD_CLK,
            DATA_OUT => DATA_OUT
        );
end generate;

stage1:
if stages=1 generate
    GEN_STAGE1: for I in 0 to 3 generate
        OR10:OR4X32_REG
            port map (
                BUSA => BANK_DATA(I*4),
                BUSB => BANK_DATA((I*4)+1),
                BUSC => BANK_DATA((I*4)+2),
                BUSD => BANK_DATA((I*4)+3),
                CLK => RD_CLK,
                DATA_OUT => TEMP_ARRAY_DATA(I)
            );
    end generate;
    OR11:OR4X32_REG
        port map (
            BUSA => TEMP_ARRAY_DATA(0),
            BUSB => TEMP_ARRAY_DATA(1),
            BUSC => TEMP_ARRAY_DATA(2),
            BUSD => TEMP_ARRAY_DATA(3),
            CLK => RD_CLK,
            DATA_OUT => DATA_OUT
        );
end generate;

stage2:
if stages=2 generate
    GEN_STAGE2: for I in 0 to 15 generate
        OR20:OR4X32_REG
            port map (
                BUSA => BANK_DATA(I*4),
                BUSB => BANK_DATA((I*4)+1),
                BUSC => BANK_DATA((I*4)+2),
                BUSD => BANK_DATA((I*4)+3),
                CLK => RD_CLK,
                DATA_OUT => TEMP_ARRAY_DATA(I)
            );
    end generate;
    GEN_STAGE3: for I in 0 to 3 generate
        OR21:OR4X32_REG
            port map (
                BUSA => TEMP_ARRAY_DATA(I*4),
                BUSB => TEMP_ARRAY_DATA((I*4)+1),
                BUSC => TEMP_ARRAY_DATA((I*4)+2),
                BUSD => TEMP_ARRAY_DATA((I*4)+3),
                CLK => RD_CLK,
                DATA_OUT => TEMP_ARRAY_DATA(I+16)
            );
    end generate;
    OR22:OR4X32_REG
        port map (
            BUSA => TEMP_ARRAY_DATA(16),
            BUSB => TEMP_ARRAY_DATA(17),
            BUSC => TEMP_ARRAY_DATA(18),
            BUSD => TEMP_ARRAY_DATA(19),
            CLK => RD_CLK,
            DATA_OUT => DATA_OUT
        );
end generate;

DELAY1: DELAY
    generic map(DELAY_LENGTH => (STAGES+1))
    port map(
	CLK => RD_CLK,
	CE => VCC,
	DIN => READ_ENABLE,
	DOUT => READ_ENABLE_OUT
    );

end OUTPUT_PIPELINE_arch;