s2p8x32.vhd

VHDL设计实例

--
-- The S2P8X32 module (Serial to Parallel convertor, 8 channels by 32 bit).  This module
-- takes eight serial input streams and outputs eight 32 bit words. It consists of a delay
-- module, eight 8X1 muxes, and thirty-two 16X1 dual-port RAMS.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;


entity S2P8X32 is
    port (
        SERIAL_DATA: in STD_LOGIC_VECTOR(7 downto 0);
        WRITE_ENABLE: in STD_LOGIC;
        WR_CLK: in STD_LOGIC;
        WRITE_ADDRESS: in WRITE_ADDRESS_ARRAY;
        MSB_WR: in STD_LOGIC_VECTOR(3 downto 0);
        DP_WR_EN: in STD_LOGIC_VECTOR(31 downto 0);
        RESET: in STD_LOGIC;
        OE: in STD_LOGIC;
        RD_CLK: in STD_LOGIC;
        READ_ENABLE: in STD_LOGIC;
        FORCE_RD_ADDRESS_INC: in STD_LOGIC;
	ADJUST_ADDRESS_MASK: in STD_LOGIC;
        DATA_BANK_OUT: out STD_LOGIC_VECTOR(31 downto 0)
    );
end S2P8X32;

architecture S2P8X32_arch of S2P8X32 is
--
-- This module causes the input signal to be delayed DELAY_LENGTH clock cycles.
-- The delays are implemented using SHIFT REGISTER LUTS.
--
component DELAY
   generic(DELAY_LENGTH: in INTEGER);
   port (
        CLK: in STD_LOGIC;
        CE: in  STD_LOGIC;
	DIN: in STD_LOGIC;
	DOUT: out STD_LOGIC
	);
end component;
--
-- Simple 8X1 mux
--
component MUX_8X1
   port (
        DIN: in STD_LOGIC_VECTOR(7 downto 0);
        SEL: in STD_LOGIC_VECTOR(2 downto 0);
        MUXOUT: out STD_LOGIC
        );
end component ;
--
-- 16x1 Dual port RAM module
--
component RAM16X1D
   port (
        WE: in STD_LOGIC;
        D: in STD_LOGIC;
        WCLK: in STD_LOGIC;
        A0: in STD_LOGIC;
        A1: in STD_LOGIC;
        A2: in STD_LOGIC;
        A3: in STD_LOGIC;
        DPRA0: in STD_LOGIC;
        DPRA1: in STD_LOGIC;
        DPRA2: in STD_LOGIC;
        DPRA3: in STD_LOGIC;
        SPO: out STD_LOGIC;
        DPO: out STD_LOGIC
        );
end component ;
--
-- Signal declarations
--
signal DELAYED_DATA:STD_LOGIC_VECTOR(7 downto 0);
signal MUXED_DATA:STD_LOGIC_VECTOR(7 downto 0);
signal READ_DATA:STD_LOGIC_VECTOR(31 downto 0);
signal REG_READ_DATA_A: STD_LOGIC_VECTOR (31 downto 0);
signal REG_READ_DATA_B: STD_LOGIC_VECTOR (31 downto 0);
signal READ_ADDRESS: STD_LOGIC_VECTOR (3 downto 0);


begin

--
-- Create eight delay lines, with delays of 0 through 7 clock cycles
--
GEN_DELAY1:
for I in 0 to 7 generate
   U1: DELAY
   generic map(DELAY_LENGTH => I)
   port map (
	CLK => WR_CLK,
	CE => WRITE_ENABLE,
	DIN => SERIAL_DATA(I),
	DOUT => DELAYED_DATA(I)
	);
end generate;
--
-- Create eight 8x1 muxes
--
GEN_DATA_MUX:
for I in 0 to 7 generate
   MUX1: MUX_8X1 port map (
       DIN => DELAYED_DATA,
       SEL => WRITE_ADDRESS(I),
       MUXOUT => MUXED_DATA(I)
       );
end generate;
--
-- Create thirty-two 16x1 dual-port RAMS, orginized as four banks of eight. Each bank
-- of eight is sourced by the eight 8x1 muxes. 
--
GEN_DPRAM1:
for I in 0 to 31 generate
   BANK0: if I < 8 generate
   RAM0: RAM16X1D
   port map (
        WE=> DP_WR_EN(I),
        D=> MUXED_DATA(I),
        WCLK=> WR_CLK,
        A0=> WRITE_ADDRESS(I)(0),
        A1=> WRITE_ADDRESS(I)(1),
        A2=> WRITE_ADDRESS(I)(2),
        A3=> MSB_WR(0),
        DPRA0=> READ_ADDRESS(0),
        DPRA1=> READ_ADDRESS(1),
        DPRA2=> READ_ADDRESS(2),
        DPRA3=> READ_ADDRESS(3),
        SPO=> OPEN,
        DPO => READ_DATA(I)
	);
   end generate;
   BANK1: if  I > 7 and I < 16 generate
   RAM1: RAM16X1D
   port map (
        WE=> DP_WR_EN(I),
        D=> MUXED_DATA(I-8),
        WCLK=> WR_CLK,
        A0=> WRITE_ADDRESS(I-8)(0),
        A1=> WRITE_ADDRESS(I-8)(1),
        A2=> WRITE_ADDRESS(I-8)(2),
        A3=> MSB_WR(1),
        DPRA0=> READ_ADDRESS(0),
        DPRA1=> READ_ADDRESS(1),
        DPRA2=> READ_ADDRESS(2),
        DPRA3=> READ_ADDRESS(3),
        SPO=> OPEN,
        DPO => READ_DATA(I)
	);
   end generate;
   BANK2: if  I > 15 and I < 24 generate
   RAM2: RAM16X1D
   port map (
        WE=> DP_WR_EN(I),
        D=> MUXED_DATA(I-16),
        WCLK=> WR_CLK,
        A0=> WRITE_ADDRESS(I-16)(0),
        A1=> WRITE_ADDRESS(I-16)(1),
        A2=> WRITE_ADDRESS(I-16)(2),
        A3=> MSB_WR(2),
        DPRA0=> READ_ADDRESS(0),
        DPRA1=> READ_ADDRESS(1),
        DPRA2=> READ_ADDRESS(2),
        DPRA3=> READ_ADDRESS(3),
        SPO=> OPEN,
        DPO => READ_DATA(I)
	);
    end generate;
   BANK3: if  I > 23 generate
   RAM3: RAM16X1D
   port map (
        WE=> DP_WR_EN(I),
        D=> MUXED_DATA(I-24),
        WCLK=> WR_CLK,
        A0=> WRITE_ADDRESS(I-24)(0),
        A1=> WRITE_ADDRESS(I-24)(1),
        A2=> WRITE_ADDRESS(I-24)(2),
        A3=> MSB_WR(3),
        DPRA0=> READ_ADDRESS(0),
        DPRA1=> READ_ADDRESS(1),
        DPRA2=> READ_ADDRESS(2),
        DPRA3=> READ_ADDRESS(3),
        SPO=> OPEN,
        DPO => READ_DATA(I)
	);
    end generate;
end generate;
--
-- Read address generation and control
--
process (RD_CLK, RESET)
begin
   if RESET='1' then
       READ_ADDRESS(3 downto 0) <= "0000";
   elsif RD_CLK='1' and RD_CLK'event then
       if READ_ENABLE='1' then
           if(OE='1' or (FORCE_RD_ADDRESS_INC='1' and ADJUST_ADDRESS_MASK= '1')) then
               READ_ADDRESS <= READ_ADDRESS + 1;
           end if;
       end if;
   end if;
end process;
--
-- Mux the N banks of dual-ports using TRI_STATE buffers
--
process (RD_CLK)
begin
   if RD_CLK='1' and RD_CLK'event then
      if READ_ENABLE = '1' then
          for I in 0 to 31 loop
              DATA_BANK_OUT(I) <= READ_DATA(I) and OE;
          end loop;
      end if;
   end if;
end process;

end S2P8X32_arch;