ser_par_lib.vhd

VHDL设计实例

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


package SER_PAR_LIB is
    constant PORTS:INTEGER := 43;
    
    constant BUS_WIDTH:INTEGER := 32;
--
-- BEFORE SETTING THE READ/WRITE STALL ENABLE BITS, SEE THE FOLLOWING DISCUSSION
--
-- ASSUME 172 CHANNELS OF 32 BIT DATA BEING CLOCKED IN AT 20 MHZ AND READ OUT AT 100 MHZ
--
-- READ RATE IS 32 BITS AT 100 MHZ OR 3200 MBS
-- WRITE RATE IS 172 BITS AT 20 MHZ OR 3440 MBS
-- 
-- THUS THE WRITE RATE IS FASTER AND ENABLE_WRITE_STALL CONSTANT MUST BE SET TO 1
--
-- IF THE RATES ARE EQUAL RESET BOTH CONATANTS TO ZERO
--

-- SET TO 1 IF READ RATE IN BPS EXCEEDS WRITE RATE IN BPS ELSE 0   
--   constant ENABLE_READ_STALL: INTEGER := 1;
    
 -- SET TO 1 IF WRITE RATE IN BPS EXCEEDS READ RATE IN BPS ELSE 0       
--    constant ENABLE_WRITE_STALL: INTEGER := 1;

--********************************************
--  Ignore the above comments.....
--  
-- Set ENABLE_READ_STALL, ENABLE_WRITE_STALL to 1 when data rates are different
--
-- Set ENABLE_READ_STALL, ENABLE_WRITE_STALL to 0 when data rates are the same
 --********************************************
constant ENABLE_READ_STALL: INTEGER := 1;
constant ENABLE_WRITE_STALL: INTEGER := 1;
    
    function DETERMINE_NUMBER_OF_BANKS(NUMBER_OF_SERIAL_PORTS: INTEGER) return INTEGER;

    constant BANKS:INTEGER := DETERMINE_NUMBER_OF_BANKS(PORTS);

    function CREATE_MASK(NUMBER_OF_SERIAL_PORTS: INTEGER; NUMBER_OF_BANKS: INTEGER) return STD_LOGIC_VECTOR;

    constant MASK: STD_LOGIC_VECTOR(BANKS-1 downto 0) := CREATE_MASK(PORTS,BANKS);

    function DETERMINE_OUTPUT_STAGES(NUMBER_OF_BANKS: INTEGER) return INTEGER;

    constant STAGES:INTEGER := DETERMINE_OUTPUT_STAGES(BANKS);
    
    type SERIAL_DATA_ARRAY is array (BANKS-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);

    type DATA_OUT_ARRAY is array (63 downto 0) of STD_LOGIC_VECTOR (31 downto 0);

    type WRITE_ADDRESS_ARRAY is array (7 downto 0) of STD_LOGIC_VECTOR (2 downto 0);

end package SER_PAR_LIB;

package body SER_PAR_LIB is
--
-- DETERMINE THE NUMBER OF BANKS
--    
    function DETERMINE_NUMBER_OF_BANKS(NUMBER_OF_SERIAL_PORTS: INTEGER) return INTEGER is
    begin
        if ((NUMBER_OF_SERIAL_PORTS mod 8) = 0) then
            return  (NUMBER_OF_SERIAL_PORTS/8);
        else
            return  (NUMBER_OF_SERIAL_PORTS+(8 - (NUMBER_OF_SERIAL_PORTS mod 8)))/8;
        end if;
    end DETERMINE_NUMBER_OF_BANKS;
    
--
-- CREATE FIX UP MASK FOR READ COUNTERS - 1 to fix up, 0 if ok
--
    function CREATE_MASK(
        NUMBER_OF_SERIAL_PORTS: INTEGER;
        NUMBER_OF_BANKS: INTEGER
    ) return STD_LOGIC_VECTOR is
        variable TEMP: STD_LOGIC_VECTOR(NUMBER_OF_BANKS - 1 downto 0);
    begin
        if ((NUMBER_OF_SERIAL_PORTS mod 8) = 0) then
            for I in 0 to NUMBER_OF_BANKS - 1 loop
                TEMP(I) := '0';
            end loop;
            return TEMP;
        else
            for I in 0 to (NUMBER_OF_SERIAL_PORTS - (7 * NUMBER_OF_BANKS) -1) loop
                TEMP(I) := '0';
            end loop;
            for I in (NUMBER_OF_SERIAL_PORTS - (7 * NUMBER_OF_BANKS)) to (NUMBER_OF_BANKS - 1) loop
                TEMP(I) := '1';
            end loop;
            return TEMP;
        end if;
    end CREATE_MASK;
--
-- DETERMINE NUMBER OF STAGES IN THE OUTPUT PIPELINE
--    
    function DETERMINE_OUTPUT_STAGES(NUMBER_OF_BANKS:INTEGER) return INTEGER is
    begin
        if (NUMBER_OF_BANKS < 5) then
            return 0;
        elsif (NUMBER_OF_BANKS < 17) then
            return 1;
        else
            return 2;
        end if;
    end DETERMINE_OUTPUT_STAGES;

end package body SER_PAR_LIB;