rd_cntrl.vhd

VHDL设计实例

--
-- Sychronizer circuit, and read control, as well as stall generation. Assumes that read port
-- cannot keep up with the write circuit, and hence generates a stall signal that disables the
-- write port.  The source of the data must stop inputing data until the stall goes away.
-- Signalling between the read and write circuits is double buffered to prevent metastability.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;


entity RD_CNTRL is
    generic(
        NUMBER_OF_BANKS: INTEGER;
        NUMBER_OF_SERIAL_PORTS: INTEGER
    );
    port (
        RESET: in STD_LOGIC;
        CLK: in STD_LOGIC;
        READ_ENABLE: in STD_LOGIC;
        DECREMENT_BCOUNT: out STD_LOGIC;
        READ_COUNT_OUT: out INTEGER;
        FORCE_RD_ADDRESS_INC: out STD_LOGIC;
        OE: out STD_LOGIC_VECTOR (NUMBER_OF_BANKS-1 downto 0)                
    );
end RD_CNTRL;

architecture RD_CNTRL_arch of RD_CNTRL is

signal READ_COUNT: INTEGER range 0 to 255; 
signal OE_INT: STD_LOGIC_VECTOR (NUMBER_OF_BANKS - 1 DOWNTO 0);

begin
--
-- Assign outputs
--
OE <= OE_INT;
READ_COUNT_OUT <= READ_COUNT;
--
-- Signal done when N words have been read, then toggle read address for next group
--
READ_CTR:
process (CLK, RESET)
begin
   if RESET='1' then				-- Asynch reset
      DECREMENT_BCOUNT <= '0';
      READ_COUNT <= 0;
   elsif CLK='1' and CLK'event then	-- Count reads
      if READ_ENABLE = '1' then
	  if (READ_COUNT = NUMBER_OF_SERIAL_PORTS-4) then
	      READ_COUNT <= READ_COUNT + 1;
	      DECREMENT_BCOUNT <= '1';
	  elsif (READ_COUNT = NUMBER_OF_SERIAL_PORTS-3) then
	      READ_COUNT <= READ_COUNT + 1;
	      DECREMENT_BCOUNT <= '0';
	  elsif (READ_COUNT = NUMBER_OF_SERIAL_PORTS-1) then
	      READ_COUNT <= 0;
	      DECREMENT_BCOUNT <= '0';
	  else      	      
	      READ_COUNT <= READ_COUNT + 1;
	      DECREMENT_BCOUNT <= '0';
	  end if;
      end if;
   end if;
end process READ_CTR;
--
--  Generate output enables for the outputs for the N banks of convertors
--
process (CLK, RESET)
begin
   if RESET='1' then
      FORCE_RD_ADDRESS_INC <='0';
      OE_INT(0) <= '1';
      for I in 1 to (NUMBER_OF_BANKS - 1) loop
      OE_INT(I) <= '0';
      end loop;
   elsif CLK='1' and CLK'event then
      if READ_ENABLE = '1' then
          if (READ_COUNT /= NUMBER_OF_SERIAL_PORTS-1) then
              FORCE_RD_ADDRESS_INC <='0';
              OE_INT(NUMBER_OF_BANKS-1 downto 0) <= OE_INT(NUMBER_OF_BANKS-2 downto 0)&OE_INT(NUMBER_OF_BANKS-1);
          else
              FORCE_RD_ADDRESS_INC <='1';
              OE_INT(0) <= '1';
              for I in 1 to (NUMBER_OF_BANKS-1) loop
                  OE_INT(I) <= '0';
              end loop;
          end if;
      end if;
   end if;
end process;
	
end RD_CNTRL_arch;