mux_8x1.vhd

VHDL设计实例

--
--  Simple 8x1 multiplexor
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library WORK1;
use WORK1.SER_PAR_LIB.all;


entity MUX_8X1 is
    port (
        DIN: in STD_LOGIC_VECTOR(7 downto 0);
        SEL: in STD_LOGIC_VECTOR(2 downto 0);
        MUXOUT: out STD_LOGIC
        );
end MUX_8X1;

architecture MUX_8X1_arch of MUX_8X1 is
begin
with SEL select
    MUXOUT <= DIN(0) when "000",	
	      DIN(1) when "001",
	      DIN(2) when "010",
	      DIN(3) when "011",
	      DIN(4) when "100",
	      DIN(5) when "101",
	      DIN(6) when "110",
	      DIN(7) when others;
end MUX_8X1_arch;