picc.ini

增加PICC支持PIC16F883,690等芯片

#	This file defines the memory sizes and organization
#	of all PIC devices
#
#	All values are in hexadecimal unless otherwise stated.
#
#	Fields used are:
#
#	ARCH=<processor_architecture>
#			PIC12, PIC14 or PIC16, corresponding to baseline,
#			midrange and high end respectively
#	PROCID=<id>
#			Microchip processor identifier. This corresponds
#			to the processor field in Microchip COFF output.
#	ROMSIZE=<size_of_rom>
#			Size of program memory (words) in hex
#	BANKS=<num_banks>
#			Number of data memory banks used (for the
#			midrange, this will always be at least 2)
#	RAMBANK=<range_start>,<range_end>
#			This field may appear multiple times and
#			specifies a RAM bank memory range. e.g. A0,BF
#	COMMON=<range_start>,<range_end>
#			Specifies an area of RAM that is mirrored in all
#			banks, i.e. is accessible regardless of RPn settings.
#	ICD1RAM=<range_start>,<range_end>
#			Specifies an area of RAM that is used by 
#			MPLAB-ICD
#	ICD2RAM=<range_start>,<range_end>
#			Specifies an area of RAM that is used by 
#			MPLAB-ICD2
#	ICD1ROM=<range_start>,<range_end>
#			Specifies an area of ROM that is used by 
#			MPLAB-ICD
#	ICD2ROM=<range_start>,<range_end>
#			Specifies an area of ROM that is used by 
#			MPLAB-ICD2
#	SPAREBIT=<bit_num>
#			The bit number of a status register bit that is
#			implemented as a read/write bit, but is ignored by
#			the processor. The RP1 bit is the usual one, on chips
#			with only 2 data memory banks.
#	DATABANK=<bank>
#			Identifies which bank the EEDATA/PMDATA register is found.
#			Used for library selection.
#
#	FLASHTYPE=<string>
#			Indicates if and how this midrange processor is capable of reading
#			and/or writing (READWRITE) its program memory.
#			READ - Read only
#			READWRITE - Can write one word at a time
#			READWRITE_A - Writes done in blocks of 4 words
#			READWRITE_B - 32-Word erasure required before writes
#
#	EEPROMSIZE=<size>
#			Identifies the size (bytes) of EEPROM available to this device
#
#	OSCCAL=<address>
#			The address where the OSCCAL sfr is located.
#			If this chip stores an oscillator calibration constant at the top
#			of program memory, the compiler can assign this to the OSCCAL sfr
#			which is located at the given address.
#

# 	Baseline Microcontrollers

# Preliminary support provided for all 10F20x parts
# Contact [e-mail] for further information.
[10F200]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F200
ROMSIZE=100
BANKS=1
RAMBANK=10-1F

[10F202]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F202
ROMSIZE=200
BANKS=1
RAMBANK=08-1F

[10F204]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F204
ROMSIZE=100
BANKS=1
RAMBANK=10-1F

[10F206]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F206
ROMSIZE=200
BANKS=1
RAMBANK=08-1F

[10F220]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F220
ROMSIZE=100
BANKS=1
RAMBANK=10-1F

[10F222]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F222
ROMSIZE=200
BANKS=1
RAMBANK=09-1F

[12C508]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=2508
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=6

[12F508]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F508
ROMSIZE=200
BANKS=1
RAMBANK=07-1F

[12C509]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=2509
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[12F509]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F509
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F

[12F510]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F510
ROMSIZE=400
BANKS=2
RAMBANK=0A-1F,30-3F
COMMON=0A-0F

[12C508A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=508A
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=6

[12C509A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=509A
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[12C509AG]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=7509
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[RF509AG]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=7509
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[12C509AF]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6509
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[RF509AF]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6509
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[12CR509A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D09A
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[12CE518]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=2518
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=6

[12CE519]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=2519
ROMSIZE=400
BANKS=2
RAMBANK=07-1F,30-3F
COMMON=07-0F
#SPAREBIT=6

[16C505]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=2505
ROMSIZE=400
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F

[16F505]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F505
ROMSIZE=400
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F

[16F506]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=F506
ROMSIZE=400
BANKS=4
RAMBANK=0D-1F,30-3F,50-5F,70-7F
COMMON=0D-0F

[16C52]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6C52
ROMSIZE=180
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16C54]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6C54
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16CR54A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D54A
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16CR54B]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D54B
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16CR54C]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D54C
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16HV540]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6540
ROMSIZE=200
BANKS=1
RAMBANK=08-1F
#SPAREBIT=7

[16C54A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=654A
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16C54B]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=654B
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16C54C]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=654C
ROMSIZE=200
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16F54]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6F54
ROMSIZE=200
BANKS=1
RAMBANK=07-1F

[16C55]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6C55
ROMSIZE=200
BANKS=1
RAMBANK=08-1F
#SPAREBIT=7

[16C55A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=655A
ROMSIZE=200
BANKS=1
RAMBANK=08-1F
#SPAREBIT=7

[16C56]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6C56
ROMSIZE=400
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16C56A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=656A
ROMSIZE=400
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16CR56A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D56A
ROMSIZE=400
BANKS=1
RAMBANK=07-1F
#SPAREBIT=7

[16C57]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6C57
ROMSIZE=800
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F
#SPAREBIT=7

[16C57C]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=657C
ROMSIZE=800
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F
#SPAREBIT=7

[16CR57B]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D57B
ROMSIZE=800
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F
#SPAREBIT=7

[16CR57C]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D57C
ROMSIZE=800
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F
#SPAREBIT=7

[16F57]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6F57
ROMSIZE=800
BANKS=4
RAMBANK=08-1F,30-3F,50-5F,70-7F
COMMON=08-0F

[16C58]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=658A
ROMSIZE=800
BANKS=4
RAMBANK=07-1F,30-3F,50-5F,70-7F
COMMON=07-0F
#SPAREBIT=7

[16C58A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=658A
ROMSIZE=800
BANKS=4
RAMBANK=07-1F,30-3F,50-5F,70-7F
COMMON=07-0F
#SPAREBIT=7

[16C58B]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=658B
ROMSIZE=800
BANKS=4
RAMBANK=07-1F,30-3F,50-5F,70-7F
COMMON=07-0F
#SPAREBIT=7

[16CR58A]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D58A
ROMSIZE=800
BANKS=4
RAMBANK=07-1F,30-3F,50-5F,70-7F
COMMON=07-0F
#SPAREBIT=7

[16CR58B]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=D58B
ROMSIZE=800
BANKS=4
RAMBANK=07-1F,30-3F,50-5F,70-7F
COMMON=07-0F
#SPAREBIT=7

[16F59]
MAKE=MICROCHIP
ARCH=PIC12
OSCCAL=5
PROCID=6F59
ROMSIZE=800
BANKS=4
#BANKS=8
RAMBANK=0A-1F,30-3F,50-5F,70-7F
#RAMBANK=90-9F,B0-BF,D0-DF,E0-EF
COMMON=0A-0F
# Note this device actually has 8 RAM banks. We'll support only four.
# It is expected that full support for 8 banks will be possible after
# the version 9.00 series compiler release.

# 	Midrange Microcontrollers

[12F609]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=F609
ROMSIZE=400
BANKS=2
RAMBANK=40-7F
COMMON=70-7F

[12HV609]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=2609
ROMSIZE=400
BANKS=2
RAMBANK=40-7F
COMMON=70-7F

[12F615]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=F615
ROMSIZE=400
BANKS=2
RAMBANK=40-7F
COMMON=70-7F

[12HV615]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=2615
ROMSIZE=400
BANKS=2
RAMBANK=40-7F
COMMON=70-7F

[12F629]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=90
PROCID=2629
ROMSIZE=400
BANKS=2
RAMBANK=20-5F
COMMON=20-5F
ICD2RAM=54-5F
ICD2ROM=300-3FE
DATABANK=1
EEPROMSIZE=80

[12F635]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=2635
ROMSIZE=400
BANKS=4
RAMBANK=40-7F
COMMON=70-7F
#SPAREBIT=6
ICD2ROM=300-3FF
ICD2RAM=65-6F,70-70
DATABANK=1
EEPROMSIZE=80

[12C671]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=85
PROCID=2671
ROMSIZE=3FF
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F

[12C672]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=85
PROCID=2672
ROMSIZE=800
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F

[12CE673]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=85
PROCID=2673
ROMSIZE=400
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F

[12CE674]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=85
PROCID=2674
ROMSIZE=800
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F

[12F675]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=90
PROCID=2675
ROMSIZE=400
BANKS=2
RAMBANK=20-5F
COMMON=20-5F
ICD2RAM=54-5F
ICD2ROM=300-3FF
DATABANK=1
EEPROMSIZE=80

[12F675F]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=90
PROCID=2675
ROMSIZE=400
BANKS=2
RAMBANK=20-5F
COMMON=20-5F
ICD2RAM=54-5F
ICD2ROM=300-3FF
DATABANK=1
EEPROMSIZE=80

[12F675H]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=90
PROCID=2675
ROMSIZE=400
BANKS=2
RAMBANK=20-5F
COMMON=20-5F
ICD2RAM=54-5F
ICD2ROM=300-3FF
DATABANK=1
EEPROMSIZE=80

[12F675K]
MAKE=MICROCHIP
ARCH=PIC14
OSCCAL=90
PROCID=2675
ROMSIZE=400
BANKS=2
RAMBANK=20-5F
COMMON=20-5F
ICD2RAM=54-5F
ICD2ROM=300-3FF
DATABANK=1
EEPROMSIZE=80

[12F683]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=F683
ROMSIZE=800
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F
ICD2RAM=65-6F,70-70
ICD2ROM=700-7FF
DATABANK=1
EEPROMSIZE=100

[14000]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=4000
ROMSIZE=FC0
BANKS=2
RAMBANK=20-7F,A0-FF
#SPAREBIT=6

[16C432]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=6432
ROMSIZE=800
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F
#SPAREBIT=6

[16C433]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=6433
ROMSIZE=800
BANKS=2
RAMBANK=20-7F,A0-BF
COMMON=70-7F

[16C554]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=6554
ROMSIZE=200
BANKS=2
RAMBANK=20-6F
#SPAREBIT=6

[16C554A]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=6554
ROMSIZE=200
BANKS=2
RAMBANK=20-6F
#SPAREBIT=6

[16C556]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=6556
ROMSIZE=400
BANKS=2
RAMBANK=20-6F
#SPAREBIT=6

[16C556A]
MAKE=MICROCHIP
ARCH=PIC14
PROCID=6556