📄 pic12f615.h
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#ifndef _HTC_H_
#warning Header file pic12f615.h included directly. Use #include <htc.h> instead.
#endif
/* header file for the MICROCHIP PIC microcontroller
12F609
12HV609
12F615
12HV615
*/
#ifndef __PIC12F615_H
#define __PIC12F615_H
// Special function register definitions
static volatile unsigned char TMR0 @ 0x001;
static volatile unsigned char PCL @ 0x002;
static volatile unsigned char STATUS @ 0x003;
static unsigned char FSR @ 0x004;
static volatile unsigned char GPIO @ 0x005;
static volatile unsigned char PCLATH @ 0x00A;
static volatile unsigned char INTCON @ 0x00B;
static volatile unsigned char PIR1 @ 0x00C;
static volatile unsigned char TMR1L @ 0x00E;
static volatile unsigned char TMR1H @ 0x00F;
static unsigned char T1CON @ 0x010;
#if defined(_12F615) || defined(_12HV615)
static volatile unsigned char TMR2 @ 0x011;
static unsigned char T2CON @ 0x012;
static volatile unsigned char CCPR1L @ 0x013;
static volatile unsigned char CCPR1H @ 0x014;
static volatile unsigned char CCP1CON @ 0x015;
static volatile unsigned char PWM1CON @ 0x016;
static volatile unsigned char ECCPAS @ 0x017;
#endif
static unsigned char VRCON @ 0x019;
static volatile unsigned char CMCON0 @ 0x01A;
static unsigned char CMCON1 @ 0x01C;
#if defined(_12F615) || defined(_12HV615)
static volatile unsigned char ADRESH @ 0x01E;
static volatile unsigned char ADCON0 @ 0x01F;
#endif
static bank1 unsigned char OPTION @ 0x081;
static volatile bank1 unsigned char TRISIO @ 0x085;
static bank1 unsigned char PIE1 @ 0x08C;
static volatile bank1 unsigned char PCON @ 0x08E;
static bank1 unsigned char OSCTUNE @ 0x090;
#if defined(_12F615) || defined(_12HV615)
static bank1 unsigned char PR2 @ 0x092;
static bank1 unsigned char APFCON @ 0x093;
#endif
static bank1 unsigned char WPU @ 0x095;
static bank1 unsigned char IOC @ 0x096;
#if defined(_12F615) || defined(_12HV615)
static volatile bank1 unsigned char ADRESL @ 0x09E;
#endif
static bank1 unsigned char ANSEL @ 0x09F;
/* Definitions for STATUS register */
static volatile bit CARRY @ ((unsigned)&STATUS*8)+0;
static volatile bit DC @ ((unsigned)&STATUS*8)+1;
static volatile bit ZERO @ ((unsigned)&STATUS*8)+2;
static volatile bit PD @ ((unsigned)&STATUS*8)+3;
static volatile bit TO @ ((unsigned)&STATUS*8)+4;
static bit RP0 @ ((unsigned)&STATUS*8)+5;
static bit RP1 @ ((unsigned)&STATUS*8)+6;
static bit IRP @ ((unsigned)&STATUS*8)+7;
/* Definitions for GPIO register */
static volatile bit GP0 @ ((unsigned)&GPIO*8)+0;
static volatile bit GP1 @ ((unsigned)&GPIO*8)+1;
static volatile bit GP2 @ ((unsigned)&GPIO*8)+2;
static volatile bit GP3 @ ((unsigned)&GPIO*8)+3;
static volatile bit GP4 @ ((unsigned)&GPIO*8)+4;
static volatile bit GP5 @ ((unsigned)&GPIO*8)+5;
/* Definitions for INTCON register */
static volatile bit GPIF @ ((unsigned)&INTCON*8)+0;
static volatile bit INTF @ ((unsigned)&INTCON*8)+1;
static volatile bit T0IF @ ((unsigned)&INTCON*8)+2;
static bit GPIE @ ((unsigned)&INTCON*8)+3;
static bit INTE @ ((unsigned)&INTCON*8)+4;
static bit T0IE @ ((unsigned)&INTCON*8)+5;
static bit PEIE @ ((unsigned)&INTCON*8)+6;
static bit GIE @ ((unsigned)&INTCON*8)+7;
/* Definitions for PIR1 register */
static volatile bit TMR1IF @ ((unsigned)&PIR1*8)+0;
#if defined(_12F615) || defined(_12HV615)
static volatile bit TMR2IF @ ((unsigned)&PIR1*8)+1;
#endif
static volatile bit CMIF @ ((unsigned)&PIR1*8)+3;
#if defined(_12F615) || defined(_12HV615)
static volatile bit CCP1IF @ ((unsigned)&PIR1*8)+5;
static volatile bit ADIF @ ((unsigned)&PIR1*8)+6;
#endif
/* Definitions for T1CON register */
static bit TMR1ON @ ((unsigned)&T1CON*8)+0;
static bit TMR1CS @ ((unsigned)&T1CON*8)+1;
static bit T1SYNC @ ((unsigned)&T1CON*8)+2;
static bit T1OSCEN @ ((unsigned)&T1CON*8)+3;
static bit T1CKPS0 @ ((unsigned)&T1CON*8)+4;
static bit T1CKPS1 @ ((unsigned)&T1CON*8)+5;
static bit TMR1GE @ ((unsigned)&T1CON*8)+6;
static bit T1GINV @ ((unsigned)&T1CON*8)+7;
#if defined(_12F615) || defined(_12HV615)
/* Definitions for T2CON register */
static bit T2CKPS0 @ ((unsigned)&T2CON*8)+0;
static bit T2CKPS1 @ ((unsigned)&T2CON*8)+1;
static bit TMR2ON @ ((unsigned)&T2CON*8)+2;
static bit TOUTPS0 @ ((unsigned)&T2CON*8)+3;
static bit TOUTPS1 @ ((unsigned)&T2CON*8)+4;
static bit TOUTPS2 @ ((unsigned)&T2CON*8)+5;
static bit TOUTPS3 @ ((unsigned)&T2CON*8)+6;
/* Definitions for CCP1CON register */
static bit CCP1M0 @ ((unsigned)&CCP1CON*8)+0;
static bit CCP1M1 @ ((unsigned)&CCP1CON*8)+1;
static bit CCP1M2 @ ((unsigned)&CCP1CON*8)+2;
static bit CCP1M3 @ ((unsigned)&CCP1CON*8)+3;
static bit DC1B0 @ ((unsigned)&CCP1CON*8)+4;
static bit DC1B1 @ ((unsigned)&CCP1CON*8)+5;
static bit P1M @ ((unsigned)&CCP1CON*8)+7;
/* Definitions for PWM1CON register */
static volatile bit PDC0 @ ((unsigned)&PWM1CON*8)+0;
static volatile bit PDC1 @ ((unsigned)&PWM1CON*8)+1;
static volatile bit PDC2 @ ((unsigned)&PWM1CON*8)+2;
static volatile bit PDC3 @ ((unsigned)&PWM1CON*8)+3;
static volatile bit PDC4 @ ((unsigned)&PWM1CON*8)+4;
static volatile bit PDC5 @ ((unsigned)&PWM1CON*8)+5;
static volatile bit PDC6 @ ((unsigned)&PWM1CON*8)+6;
static volatile bit PRSEN @ ((unsigned)&PWM1CON*8)+7;
/* Definitions for ECCPAS register */
static bit PSSBD0 @ ((unsigned)&ECCPAS*8)+0;
static bit PSSBD1 @ ((unsigned)&ECCPAS*8)+1;
static bit PSSAC0 @ ((unsigned)&ECCPAS*8)+2;
static bit PSSAC1 @ ((unsigned)&ECCPAS*8)+3;
static bit ECCPAS0 @ ((unsigned)&ECCPAS*8)+4;
static bit ECCPAS1 @ ((unsigned)&ECCPAS*8)+5;
static bit ECCPAS2 @ ((unsigned)&ECCPAS*8)+6;
static volatile bit ECCPASE @ ((unsigned)&ECCPAS*8)+7;
#endif
/* Definitions for VRCON register */
static bit VR0 @ ((unsigned)&VRCON*8)+0;
static bit VR1 @ ((unsigned)&VRCON*8)+1;
static bit VR2 @ ((unsigned)&VRCON*8)+2;
static bit VR3 @ ((unsigned)&VRCON*8)+3;
static bit FVREN @ ((unsigned)&VRCON*8)+4;
static bit VRR @ ((unsigned)&VRCON*8)+5;
static bit CMVREN @ ((unsigned)&VRCON*8)+7;
/* Definitions for CMCON0 register */
static bit CMCH @ ((unsigned)&CMCON0*8)+0;
static bit CMR @ ((unsigned)&CMCON0*8)+2;
static bit CMPOL @ ((unsigned)&CMCON0*8)+4;
static bit CMOE @ ((unsigned)&CMCON0*8)+5;
static volatile bit COUT @ ((unsigned)&CMCON0*8)+6;
static bit CMON @ ((unsigned)&CMCON0*8)+7;
/* Definitions for CMCON1 register */
static bit CMSYNC @ ((unsigned)&CMCON1*8)+0;
static bit T1GSS @ ((unsigned)&CMCON1*8)+1;
static bit CMHYS @ ((unsigned)&CMCON1*8)+3;
static bit T1ACS @ ((unsigned)&CMCON1*8)+4;
#if defined(_12F615) || defined(_12HV615)
/* Definitions for ADCON0 register */
static bit ADON @ ((unsigned)&ADCON0*8)+0;
static volatile bit GODONE @ ((unsigned)&ADCON0*8)+1;
static bit CHS0 @ ((unsigned)&ADCON0*8)+2;
static bit CHS1 @ ((unsigned)&ADCON0*8)+3;
static bit CHS2 @ ((unsigned)&ADCON0*8)+4;
static bit VCFG @ ((unsigned)&ADCON0*8)+6;
static bit ADFM @ ((unsigned)&ADCON0*8)+7;
#endif
/* Definitions for OPTION register */
static bank1 bit PS0 @ ((unsigned)&OPTION*8)+0;
static bank1 bit PS1 @ ((unsigned)&OPTION*8)+1;
static bank1 bit PS2 @ ((unsigned)&OPTION*8)+2;
static bank1 bit PSA @ ((unsigned)&OPTION*8)+3;
static bank1 bit T0SE @ ((unsigned)&OPTION*8)+4;
static bank1 bit T0CS @ ((unsigned)&OPTION*8)+5;
static bank1 bit INTEDG @ ((unsigned)&OPTION*8)+6;
static bank1 bit GPPU @ ((unsigned)&OPTION*8)+7;
/* Definitions for TRISIO register */
static volatile bank1 bit TRISIO0 @ ((unsigned)&TRISIO*8)+0;
static volatile bank1 bit TRISIO1 @ ((unsigned)&TRISIO*8)+1;
static volatile bank1 bit TRISIO2 @ ((unsigned)&TRISIO*8)+2;
static volatile bank1 bit TRISIO3 @ ((unsigned)&TRISIO*8)+3;
static volatile bank1 bit TRISIO4 @ ((unsigned)&TRISIO*8)+4;
static volatile bank1 bit TRISIO5 @ ((unsigned)&TRISIO*8)+5;
/* Definitions for PIE1 register */
static bank1 bit TMR1IE @ ((unsigned)&PIE1*8)+0;
#if defined(_12F615) || defined(_12HV615)
static bank1 bit TMR2IE @ ((unsigned)&PIE1*8)+1;
#endif
static bank1 bit CMIE @ ((unsigned)&PIE1*8)+3;
#if defined(_12F615) || defined(_12HV615)
static bank1 bit CCP1IE @ ((unsigned)&PIE1*8)+5;
static bank1 bit ADIE @ ((unsigned)&PIE1*8)+6;
#endif
/* Definitions for PCON register */
static volatile bank1 bit BOR @ ((unsigned)&PCON*8)+0;
static volatile bank1 bit POR @ ((unsigned)&PCON*8)+1;
#if defined(_12F615) || defined(_12HV615)
/* Definitions for APFCON register */
static bank1 bit P1ASEL @ ((unsigned)&APFCON*8)+0;
static bank1 bit P1BSEL @ ((unsigned)&APFCON*8)+1;
static bank1 bit T1GSEL @ ((unsigned)&APFCON*8)+4;
#endif
/* Definitions for WPU register */
static bank1 bit WPU0 @ ((unsigned)&WPU*8)+0;
static bank1 bit WPU1 @ ((unsigned)&WPU*8)+1;
static bank1 bit WPU2 @ ((unsigned)&WPU*8)+2;
static bank1 bit WPU4 @ ((unsigned)&WPU*8)+4;
static bank1 bit WPU5 @ ((unsigned)&WPU*8)+5;
/* Definitions for IOC register */
static bank1 bit IOC0 @ ((unsigned)&IOC*8)+0;
static bank1 bit IOC1 @ ((unsigned)&IOC*8)+1;
static bank1 bit IOC2 @ ((unsigned)&IOC*8)+2;
static bank1 bit IOC3 @ ((unsigned)&IOC*8)+3;
static bank1 bit IOC4 @ ((unsigned)&IOC*8)+4;
static bank1 bit IOC5 @ ((unsigned)&IOC*8)+5;
/* Definitions for ANSEL register */
static bank1 bit ANS0 @ ((unsigned)&ANSEL*8)+0;
static bank1 bit ANS1 @ ((unsigned)&ANSEL*8)+1;
#if defined(_12F615) || defined(_12HV615)
static bank1 bit ANS2 @ ((unsigned)&ANSEL*8)+2;
#endif
static bank1 bit ANS3 @ ((unsigned)&ANSEL*8)+3;
#if defined(_12F615) || defined(_12HV615)
static bank1 bit ADCS0 @ ((unsigned)&ANSEL*8)+4;
static bank1 bit ADCS1 @ ((unsigned)&ANSEL*8)+5;
static bank1 bit ADCS2 @ ((unsigned)&ANSEL*8)+6;
#endif
// Configuration Mask Definitions
#define CONFIG_ADDR 0x2007
// Brown-out detect modes
#define BOREN 0x3FFF
#define BOREN_XSLP 0x3EFF
#define BORDIS 0x3DFF
// Internal Oscillator Frequecy Select
#define OSC_8MHZ 0x3FFF
#define OSC_4MHZ 0x3FDF
// Protection of program code
#define UNPROTECT 0x3FFF
#define PROTECT 0x3FBF
// Memory clear enable
#define MCLREN 0x3FFF
#define MCLRDIS 0x3FDF
// Power up timer enable
#define PWRTDIS 0x3FFF
#define PWRTEN 0x3FEF
// Watchdog timer enable
#define WDTEN 0x3FFF
#define WDTDIS 0x3FF7
// Oscillator configurations
#define RCCLK 0x3FFF
#define RCIO 0x3FFE
#define INTCLK 0x3FFD
#define INTIO 0x3FFC
#define EC 0x3FFB
#define HS 0x3FFA
#define XT 0x3FF9
#define LP 0x3FF8
#endif
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