📄 pic16f887.h
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static volatile bank1 bit TRISD1 @ ((unsigned)&TRISD*8)+1;
static volatile bank1 bit TRISD2 @ ((unsigned)&TRISD*8)+2;
static volatile bank1 bit TRISD3 @ ((unsigned)&TRISD*8)+3;
static volatile bank1 bit TRISD4 @ ((unsigned)&TRISD*8)+4;
static volatile bank1 bit TRISD5 @ ((unsigned)&TRISD*8)+5;
static volatile bank1 bit TRISD6 @ ((unsigned)&TRISD*8)+6;
static volatile bank1 bit TRISD7 @ ((unsigned)&TRISD*8)+7;
/* Definitions for TRISE register */
static volatile bank1 bit TRISE0 @ ((unsigned)&TRISE*8)+0;
static volatile bank1 bit TRISE1 @ ((unsigned)&TRISE*8)+1;
static volatile bank1 bit TRISE2 @ ((unsigned)&TRISE*8)+2;
#endif
static volatile bank1 bit TRISE3 @ ((unsigned)&TRISE*8)+3;
/* Definitions for PIE1 register */
static bank1 bit TMR1IE @ ((unsigned)&PIE1*8)+0;
static bank1 bit TMR2IE @ ((unsigned)&PIE1*8)+1;
static bank1 bit CCP1IE @ ((unsigned)&PIE1*8)+2;
static bank1 bit SSPIE @ ((unsigned)&PIE1*8)+3;
static bank1 bit TXIE @ ((unsigned)&PIE1*8)+4;
static bank1 bit RCIE @ ((unsigned)&PIE1*8)+5;
static bank1 bit ADIE @ ((unsigned)&PIE1*8)+6;
/* Definitions for PIE2 register */
static bank1 bit CCP2IE @ ((unsigned)&PIE2*8)+0;
static bank1 bit ULPWUIE @ ((unsigned)&PIE2*8)+2;
static bank1 bit BCLIE @ ((unsigned)&PIE2*8)+3;
static bank1 bit EEIE @ ((unsigned)&PIE2*8)+4;
static bank1 bit C1IE @ ((unsigned)&PIE2*8)+5;
static bank1 bit C2IE @ ((unsigned)&PIE2*8)+6;
static bank1 bit OSFIE @ ((unsigned)&PIE2*8)+7;
/* Definitions for PCON register */
static volatile bank1 bit BOR @ ((unsigned)&PCON*8)+0;
static volatile bank1 bit POR @ ((unsigned)&PCON*8)+1;
static bank1 bit SBOREN @ ((unsigned)&PCON*8)+4;
static bank1 bit ULPWUE @ ((unsigned)&PCON*8)+5;
/* Definitions for OSCCON register */
static bank1 bit SCS @ ((unsigned)&OSCCON*8)+0;
static volatile bank1 bit LTS @ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit HTS @ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit OSTS @ ((unsigned)&OSCCON*8)+3;
static bank1 bit IRCF0 @ ((unsigned)&OSCCON*8)+4;
static bank1 bit IRCF1 @ ((unsigned)&OSCCON*8)+5;
static bank1 bit IRCF2 @ ((unsigned)&OSCCON*8)+6;
/* Definitions for OSCTUNE register */
static bank1 bit TUN0 @ ((unsigned)&OSCTUNE*8)+0;
static bank1 bit TUN1 @ ((unsigned)&OSCTUNE*8)+1;
static bank1 bit TUN2 @ ((unsigned)&OSCTUNE*8)+2;
static bank1 bit TUN3 @ ((unsigned)&OSCTUNE*8)+3;
static bank1 bit TUN4 @ ((unsigned)&OSCTUNE*8)+4;
/* Definitions for SSPCON2 register */
static bank1 bit SEN @ ((unsigned)&SSPCON2*8)+0;
static volatile bank1 bit RSEN @ ((unsigned)&SSPCON2*8)+1;
static volatile bank1 bit PEN @ ((unsigned)&SSPCON2*8)+2;
static volatile bank1 bit RCEN @ ((unsigned)&SSPCON2*8)+3;
static volatile bank1 bit ACKEN @ ((unsigned)&SSPCON2*8)+4;
static volatile bank1 bit ACKDT @ ((unsigned)&SSPCON2*8)+5;
static volatile bank1 bit ACKSTAT @ ((unsigned)&SSPCON2*8)+6;
static bank1 bit GCEN @ ((unsigned)&SSPCON2*8)+7;
/* Definitions for SSPSTAT register */
static volatile bank1 bit BF @ ((unsigned)&SSPSTAT*8)+0;
static volatile bank1 bit UA @ ((unsigned)&SSPSTAT*8)+1;
static volatile bank1 bit RW @ ((unsigned)&SSPSTAT*8)+2;
static volatile bank1 bit START @ ((unsigned)&SSPSTAT*8)+3;
static volatile bank1 bit STOP @ ((unsigned)&SSPSTAT*8)+4;
static volatile bank1 bit DA @ ((unsigned)&SSPSTAT*8)+5;
static bank1 bit CKE @ ((unsigned)&SSPSTAT*8)+6;
static bank1 bit SMP @ ((unsigned)&SSPSTAT*8)+7;
/* Definitions for WPUB register */
static bank1 bit WPUB0 @ ((unsigned)&WPUB*8)+0;
static bank1 bit WPUB1 @ ((unsigned)&WPUB*8)+1;
static bank1 bit WPUB2 @ ((unsigned)&WPUB*8)+2;
static bank1 bit WPUB3 @ ((unsigned)&WPUB*8)+3;
static bank1 bit WPUB4 @ ((unsigned)&WPUB*8)+4;
static bank1 bit WPUB5 @ ((unsigned)&WPUB*8)+5;
static bank1 bit WPUB6 @ ((unsigned)&WPUB*8)+6;
static bank1 bit WPUB7 @ ((unsigned)&WPUB*8)+7;
/* Definitions for IOCB register */
static bank1 bit IOCB0 @ ((unsigned)&IOCB*8)+0;
static bank1 bit IOCB1 @ ((unsigned)&IOCB*8)+1;
static bank1 bit IOCB2 @ ((unsigned)&IOCB*8)+2;
static bank1 bit IOCB3 @ ((unsigned)&IOCB*8)+3;
static bank1 bit IOCB4 @ ((unsigned)&IOCB*8)+4;
static bank1 bit IOCB5 @ ((unsigned)&IOCB*8)+5;
static bank1 bit IOCB6 @ ((unsigned)&IOCB*8)+6;
static bank1 bit IOCB7 @ ((unsigned)&IOCB*8)+7;
/* Definitions for VRCON register */
static bank1 bit VR0 @ ((unsigned)&VRCON*8)+0;
static bank1 bit VR1 @ ((unsigned)&VRCON*8)+1;
static bank1 bit VR2 @ ((unsigned)&VRCON*8)+2;
static bank1 bit VR3 @ ((unsigned)&VRCON*8)+3;
static bank1 bit VRSS @ ((unsigned)&VRCON*8)+4;
static bank1 bit VRR @ ((unsigned)&VRCON*8)+5;
static bank1 bit VROE @ ((unsigned)&VRCON*8)+6;
static bank1 bit VREN @ ((unsigned)&VRCON*8)+7;
/* Definitions for TXSTA register */
static volatile bank1 bit TX9D @ ((unsigned)&TXSTA*8)+0;
static volatile bank1 bit TRMT @ ((unsigned)&TXSTA*8)+1;
static bank1 bit BRGH @ ((unsigned)&TXSTA*8)+2;
static bank1 bit SENDB @ ((unsigned)&TXSTA*8)+3;
static bank1 bit SYNC @ ((unsigned)&TXSTA*8)+4;
static bank1 bit TXEN @ ((unsigned)&TXSTA*8)+5;
static bank1 bit TX9 @ ((unsigned)&TXSTA*8)+6;
static bank1 bit CSRC @ ((unsigned)&TXSTA*8)+7;
/* Definitions for SPBRG register */
static bank1 bit BRG0 @ ((unsigned)&SPBRG*8)+0;
static bank1 bit BRG1 @ ((unsigned)&SPBRG*8)+1;
static bank1 bit BRG2 @ ((unsigned)&SPBRG*8)+2;
static bank1 bit BRG3 @ ((unsigned)&SPBRG*8)+3;
static bank1 bit BRG4 @ ((unsigned)&SPBRG*8)+4;
static bank1 bit BRG5 @ ((unsigned)&SPBRG*8)+5;
static bank1 bit BRG6 @ ((unsigned)&SPBRG*8)+6;
static bank1 bit BRG7 @ ((unsigned)&SPBRG*8)+7;
/* Definitions for SPBRGH register */
static bank1 bit BRG8 @ ((unsigned)&SPBRGH*8)+0;
static bank1 bit BRG9 @ ((unsigned)&SPBRGH*8)+1;
static bank1 bit BRG10 @ ((unsigned)&SPBRGH*8)+2;
static bank1 bit BRG11 @ ((unsigned)&SPBRGH*8)+3;
static bank1 bit BRG12 @ ((unsigned)&SPBRGH*8)+4;
static bank1 bit BRG13 @ ((unsigned)&SPBRGH*8)+5;
static bank1 bit BRG14 @ ((unsigned)&SPBRGH*8)+6;
static bank1 bit BRG15 @ ((unsigned)&SPBRGH*8)+7;
/* Definitions for PWM1CON register */
static volatile bank1 bit PDC0 @ ((unsigned)&PWM1CON*8)+0;
static volatile bank1 bit PDC1 @ ((unsigned)&PWM1CON*8)+1;
static volatile bank1 bit PDC2 @ ((unsigned)&PWM1CON*8)+2;
static volatile bank1 bit PDC3 @ ((unsigned)&PWM1CON*8)+3;
static volatile bank1 bit PDC4 @ ((unsigned)&PWM1CON*8)+4;
static volatile bank1 bit PDC5 @ ((unsigned)&PWM1CON*8)+5;
static volatile bank1 bit PDC6 @ ((unsigned)&PWM1CON*8)+6;
static volatile bank1 bit PRSEN @ ((unsigned)&PWM1CON*8)+7;
/* Definitions for ECCPAS register */
static bank1 bit PSSBD0 @ ((unsigned)&ECCPAS*8)+0;
static bank1 bit PSSBD1 @ ((unsigned)&ECCPAS*8)+1;
static bank1 bit PSSAC0 @ ((unsigned)&ECCPAS*8)+2;
static bank1 bit PSSAC1 @ ((unsigned)&ECCPAS*8)+3;
static bank1 bit ECCPAS0 @ ((unsigned)&ECCPAS*8)+4;
static bank1 bit ECCPAS1 @ ((unsigned)&ECCPAS*8)+5;
static bank1 bit ECCPAS2 @ ((unsigned)&ECCPAS*8)+6;
static volatile bank1 bit ECCPASE @ ((unsigned)&ECCPAS*8)+7;
/* Definitions for PSTRCON register */
static bank1 bit STRA @ ((unsigned)&PSTRCON*8)+0;
static bank1 bit STRB @ ((unsigned)&PSTRCON*8)+1;
static bank1 bit STRC @ ((unsigned)&PSTRCON*8)+2;
static bank1 bit STRD @ ((unsigned)&PSTRCON*8)+3;
static bank1 bit STRSYNC @ ((unsigned)&PSTRCON*8)+4;
/* Definitions for ADCON1 register */
static bank1 bit VCFG0 @ ((unsigned)&ADCON1*8)+4;
static bank1 bit VCFG1 @ ((unsigned)&ADCON1*8)+5;
static bank1 bit ADFM @ ((unsigned)&ADCON1*8)+7;
/* Definitions for WDTCON register */
static bank2 bit SWDTEN @ ((unsigned)&WDTCON*8)+0;
static bank2 bit WDTPS0 @ ((unsigned)&WDTCON*8)+1;
static bank2 bit WDTPS1 @ ((unsigned)&WDTCON*8)+2;
static bank2 bit WDTPS2 @ ((unsigned)&WDTCON*8)+3;
static bank2 bit WDTPS3 @ ((unsigned)&WDTCON*8)+4;
/* Definitions for CM1CON0 register */
static bank2 bit C1CH0 @ ((unsigned)&CM1CON0*8)+0;
static bank2 bit C1CH1 @ ((unsigned)&CM1CON0*8)+1;
static bank2 bit C1R @ ((unsigned)&CM1CON0*8)+2;
static bank2 bit C1POL @ ((unsigned)&CM1CON0*8)+4;
static bank2 bit C1OE @ ((unsigned)&CM1CON0*8)+5;
static volatile bank2 bit C1OUT @ ((unsigned)&CM1CON0*8)+6;
static bank2 bit C1ON @ ((unsigned)&CM1CON0*8)+7;
/* Definitions for CM2CON0 register */
static bank2 bit C2CH0 @ ((unsigned)&CM2CON0*8)+0;
static bank2 bit C2CH1 @ ((unsigned)&CM2CON0*8)+1;
static bank2 bit C2R @ ((unsigned)&CM2CON0*8)+2;
static bank2 bit C2POL @ ((unsigned)&CM2CON0*8)+4;
static bank2 bit C2OE @ ((unsigned)&CM2CON0*8)+5;
static volatile bank2 bit C2OUT @ ((unsigned)&CM2CON0*8)+6;
static bank2 bit C2ON @ ((unsigned)&CM2CON0*8)+7;
/* Definitions for CM2CON1 register */
static bank2 bit C2SYNC @ ((unsigned)&CM2CON1*8)+0;
static bank2 bit T1GSS @ ((unsigned)&CM2CON1*8)+1;
static bank2 bit C2RSEL @ ((unsigned)&CM2CON1*8)+4;
static bank2 bit C1RSEL @ ((unsigned)&CM2CON1*8)+5;
static volatile bank2 bit MC2OUT @ ((unsigned)&CM2CON1*8)+6;
static volatile bank2 bit MC1OUT @ ((unsigned)&CM2CON1*8)+7;
/* Definitions for SRCON register */
static bank3 bit FVREN @ ((unsigned)&SRCON*8)+0;
static volatile bank3 bit PULSR @ ((unsigned)&SRCON*8)+2;
static volatile bank3 bit PULSS @ ((unsigned)&SRCON*8)+3;
static bank3 bit C2REN @ ((unsigned)&SRCON*8)+4;
static bank3 bit C1SEN @ ((unsigned)&SRCON*8)+5;
static bank3 bit SR0 @ ((unsigned)&SRCON*8)+6;
static bank3 bit SR1 @ ((unsigned)&SRCON*8)+7;
/* Definitions for BAUDCTL register */
static volatile bank3 bit ABDEN @ ((unsigned)&BAUDCTL*8)+0;
static volatile bank3 bit WUE @ ((unsigned)&BAUDCTL*8)+1;
static bank3 bit BRG16 @ ((unsigned)&BAUDCTL*8)+3;
static volatile bank3 bit SCKP @ ((unsigned)&BAUDCTL*8)+4;
static volatile bank3 bit RCIDL @ ((unsigned)&BAUDCTL*8)+6;
static volatile bank3 bit ABDOVF @ ((unsigned)&BAUDCTL*8)+7;
/* Definitions for ANSEL register */
static bank3 bit ANS0 @ ((unsigned)&ANSEL*8)+0;
static bank3 bit ANS1 @ ((unsigned)&ANSEL*8)+1;
static bank3 bit ANS2 @ ((unsigned)&ANSEL*8)+2;
static bank3 bit ANS3 @ ((unsigned)&ANSEL*8)+3;
static bank3 bit ANS4 @ ((unsigned)&ANSEL*8)+4;
#if defined(_16F884) || defined(_16F887)
static bank3 bit ANS5 @ ((unsigned)&ANSEL*8)+5;
static bank3 bit ANS6 @ ((unsigned)&ANSEL*8)+6;
static bank3 bit ANS7 @ ((unsigned)&ANSEL*8)+7;
#endif
/* Definitions for ANSELH register */
static bank3 bit ANS8 @ ((unsigned)&ANSELH*8)+0;
static bank3 bit ANS9 @ ((unsigned)&ANSELH*8)+1;
static bank3 bit ANS10 @ ((unsigned)&ANSELH*8)+2;
static bank3 bit ANS11 @ ((unsigned)&ANSELH*8)+3;
static bank3 bit ANS12 @ ((unsigned)&ANSELH*8)+4;
static bank3 bit ANS13 @ ((unsigned)&ANSELH*8)+5;
/* Definitions for EECON1 register */
static volatile bank3 bit RD @ ((unsigned)&EECON1*8)+0;
static volatile bank3 bit WR @ ((unsigned)&EECON1*8)+1;
static bank3 bit WREN @ ((unsigned)&EECON1*8)+2;
static volatile bank3 bit WRERR @ ((unsigned)&EECON1*8)+3;
static bank3 bit EEPGD @ ((unsigned)&EECON1*8)+7;
// Configuration Mask Definitions
#define CONFIG_ADDR 0x2007
// Oscillator
#define EXTCLK 0x3FFF // External RC Clockout
#define EXTIO 0x3FFE // External RC No Clock
#define INTCLK 0x3FFD // Internal RC Clockout
#define INTIO 0x3FFC // Internal RC No Clock
#define EC 0x3FFB // EC
#define HS 0x3FFA // HS
#define XT 0x3FF9 // XT
#define LP 0x3FF8 // LP
// Watchdog Timer
#define WDTEN 0x3FFF // On
#define WDTDIS 0x3FF7 // Disabled / SWDTEN control
// Power Up Timer
#define PWRTDIS 0x3FFF // Off
#define PWRTEN 0x3FEF // On
// Master Clear Enable
#define MCLREN 0x3FFF // MCLR function is enabled
#define MCLRDIS 0x3FDF // MCLR functions as IO
// Code Protect
#define UNPROTECT 0x3FFF // Code is not protected
#define CP 0x3FBF // Code is protected
// Data EE Read Protect
#define DUNPROTECT 0x3FFF // Do not read protect EEPROM data
#define CPD 0x3F7F // Read protect EEPROM data
// Brown Out Detect
#define BORDIS 0x3CFF // BOD and SBOREN disabled
#define SWBOREN 0x3DFF // SBOREN controls BOR function (Software control)
#define BORXSLP 0x3EFF // BOD enabled in run, disabled in sleep, SBOREN disabled
#define BOREN 0x3FFF // BOD Enabled, SBOREN Disabled
// Internal External Switch Over Mode
#define IESOEN 0x3FFF // Enabled
#define IESODIS 0x3BFF // Disabled
// Monitor Clock Fail-safe
#define FCMEN 0x3FFF // Enabled
#define FCMDIS 0x37FF // Disabled
// Low Voltage Programming
#define LVPDIS 0x2FFF // Disabled
#define LVPEN 0x3FFF // Enabled
// In-Circuit Debugger Mode
#define DEBUGEN 0x1FFF // Enable ICD2 debugging
#define DEBUGDIS 0x3FFF // Disable ICD2 debugging
#define CONFIG_ADDR2 0x2008
// Brown-out Reset Voltage
#define BORV21 0x3EFF // 2.1 Volts
#define BORV40 0x3FFF // 4.0 Volts
// Flash Memory Write Protection
#define WP0 0x3DFF // Protect 0h-0FFh
#define WP1 0x3BFF // Protect lower half of flash
#define WP2 0x39FF // Protect all of flash
#endif
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