mult.v

来自「8bit alu use verilog hdl」· Verilog 代码 · 共 12 行

module mult(a, b, c);
input [7:0] a, b;
output [7:0] c;
wire [7:0] c;

wire [16:0] c_tmp;

assign c_tmp = a[7:0] * b[7:0];
assign c = c_tmp[16:9];

endmodule