sreset.c

s3c2410 software reset code

#include <stdio.h>
#include <string.h>
#include "def.h"
#include "option.h"
#include "2410addr.h"
#include "2410lib.h"
#include "Sreset.h"
#include "timer.h"

#define	SDRAM_STARTADDRESS	0x30000000
#define	SDRAM_ENDADDRESS		0x33ffffff

void (*EnterSreset)(void)=(void (*)(void))0x30000040;

extern void CLR_IF(void);
extern void __irq Wdt_Int(void);

void Verify_Sdram_Data(void);
void Write_Sdram_Data(void);
void Watchdog_Set(void);
void Burst_Refresh(void);


void Test_Sreset(void)
{
	U32 i=0;
	
	Uart_Printf("=== Soft Reset test. ===\n");

	// Check Soft reset is OK, with checking the last SDRAM data is prereserved after soft reset.
	// This test is only valid when boot is caused from Watch-dog reset.
	Uart_Printf("Verify SDRAM data.\n");
	Verify_Sdram_Data();
	Uart_Printf("Press any key to continue.\n");
	Uart_Getch();

	// Write data to SDRAM to verify wheather the soft reset is performed correctly.
	Write_Sdram_Data();

	// Burst refresh with reading all SDRAM area.
	Burst_Refresh();

	// Mask F bit, I bit.
	CLR_IF();
	
	// Set watch dog reset. After this function, watch-dog reset will occure after 500ms.
	Watchdog_Set();


	Uart_Printf("\nNow Performing Soft Reset!!!.\n\n\n");
	// Set memory with self refresh and enable watchdog reset.
	EnterSreset();
		
}



void Burst_Refresh(void)
{
	U32 i;

	Uart_Printf("Burst refresh.\n");
	
	for(i=SDRAM_STARTADDRESS; i<SDRAM_ENDADDRESS; i+=8192) 	// Row addr is 13 bit.
		*(U32 *) i;
}

void Verify_Sdram_Data(void)
{
	int i, error=0;
	

	//Uart_Printf("Read saved SDRAM data.\n");
	for(i=_NONCACHE_STARTADDRESS;i<(_NONCACHE_STARTADDRESS+0x400000);i+=4) {
		if(*((U32 *)i)!=(i^0x55555555)) {
			Uart_Printf("Mem Error:%x [R:%x,W:%x]\n", i,*((U32 *)i),i^0x55555555);
			error++;
		}
		if(error>20)break;
	}
	
	if(error) Uart_Printf("SDRAM self-refresh test:FAILED\n"); 
	else Uart_Printf("SDRAM self-refresh test:O.K.\n");	

	//Uart_Printf("Clear SDRAM with 0 for next.\n");	
	for(i=_NONCACHE_STARTADDRESS;i<(_NONCACHE_STARTADDRESS+0x400000);i+=4) *((U32 *)i)=i^0x00000000;

}

void Write_Sdram_Data(void)
//Initialize SDRAM for SDRAM self-refresh test.
{
	int i;
	
	Uart_Printf("Write SDRAM data.\n");

	for(i=_NONCACHE_STARTADDRESS;i<(_NONCACHE_STARTADDRESS+0x400000);i+=4) *((U32 *)i)=i^0x55555555;
}

//================================================
// Watch-dog timer Interrupt Request Test
//================================================
extern volatile int isWdtInt;
#define	WATCHDOG_TIME	(128)	// [usec], Max=65535*128us.

void Watchdog_Set(void)
{
	int i;
	
	  //t_watchdog = 1 / (PCLK / (Prescaler value + 1 ) / Division_factor)
	Uart_Printf("Set WatchDog Timer for Soft-Reset.\n");
	
	rINTMSK  &= ~(BIT_WDT);		   //Watch dog Interrupt service is available
		
	pISR_WDT = (unsigned)Wdt_Int;
	isWdtInt = 0;

#if 0
	rWTCON = ((PCLK/1000000-1)<<8) | (3<<3) | 1<<2 | 0<<0;  //Prescaler=0x31(49),Clock division 128,Reset enable
	rWTDAT   = WATCHDOG_TIME/128;
	rWTCNT = WATCHDOG_TIME/128;		// (xsec/128us)
	rWTCON   = rWTCON | (1<<5);   //Watch-dog timer enable
	while(isWdtInt != 10);
#endif

	rWTCON = ((PCLK/1000000-1)<<8) | (3<<3) | (1);  //Prescaler=0x31(49),Clock division 128,Reset enable
	// 1*128 usec.
	  
	Uart_Printf("Set Watchdog reset time as %.1f usec.\n", (float)(WATCHDOG_TIME));
	rWTDAT   = WATCHDOG_TIME/128;
	rWTCNT = WATCHDOG_TIME/128;		// (xsec/128us)

	// The watchdog timer will be enabled in EnterSreset() in 2420init.s
}