buf2410.rpt

smdk2410 cpld code s3c2410 demo board cpld code

         #  _LC012
         # !_LC009
         #  _LC008;

-- Node name is 'nEXTBUS' = '|BUFCTRL:b0|:18' 
-- Equation name is 'nEXTBUS', type is output 
 nEXTBUS = LCELL( _EQ008 $  GND);
  _EQ008 =  nFRE &  nFWE &  nGCS0 &  nGCS1 &  nGCS2 &  nGCS3 &  nGCS4 & 
              nGCS5 &  nGCS6;

-- Node name is 'nWAIT_OD' 
-- Equation name is 'nWAIT_OD', location is LC016, type is output.
nWAIT_OD = OPNDRN(_LC016);
_LC016   = LCELL( _EQ009 $  VCC);
  _EQ009 = !_LC028 & !nGCS4 &  _X001;
  _X001  = EXP(!_LC020 & !_LC025);

-- Node name is '|DMATEST:m0|:205' = '|DMATEST:m0|counter0' 
-- Equation name is '_LC010', type is buried 
_LC010   = DFFE( _EQ010 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ010 =  _LC006 &  _LC010
         #  _LC009 &  _LC010
         # !_LC008 &  _LC010 & !_LC012
         #  _LC008 &  _LC010 &  _LC012
         # !_LC006 & !_LC008 & !_LC010 &  _LC012;

-- Node name is '|DMATEST:m0|:204' = '|DMATEST:m0|counter1' 
-- Equation name is '_LC003', type is buried 
_LC003   = TFFE( _EQ011, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ011 = !_LC006 & !_LC008 & !_LC009 & !_LC010 &  _LC012
         #  _LC003 & !_LC006 & !_LC008 &  _LC009 &  _LC012
         #  _LC003 & !_LC006 &  _LC008 & !_LC009 & !_LC012;

-- Node name is '|DMATEST:m0|:203' = '|DMATEST:m0|counter2' 
-- Equation name is '_LC002', type is buried 
_LC002   = TFFE( _EQ012, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ012 = !_LC003 & !_LC006 & !_LC008 & !_LC009 & !_LC010 &  _LC012
         #  _LC002 & !_LC006 &  _LC008 & !_LC009 & !_LC012
         #  _LC002 & !_LC006 & !_LC008 &  _LC009 &  _LC012;

-- Node name is '|DMATEST:m0|:202' = '|DMATEST:m0|counter3' 
-- Equation name is '_LC004', type is buried 
_LC004   = TFFE( _EQ013, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ013 = !_LC002 & !_LC003 & !_LC006 & !_LC008 & !_LC009 & !_LC010 & 
              _LC012
         #  _LC004 & !_LC006 &  _LC008 & !_LC009 & !_LC012
         #  _LC004 & !_LC006 & !_LC008 &  _LC009 &  _LC012;

-- Node name is '|DMATEST:m0|:77' = '|DMATEST:m0|snDACK' 
-- Equation name is '_LC029', type is buried 
_LC029   = DFFE( nDACK $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is '|DMATEST:m0|:20' = '|DMATEST:m0|snDmaStart' 
-- Equation name is '_LC013', type is buried 
_LC013   = DFFE( nDmaStart $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is '|DMATEST:m0|~291~1' 
-- Equation name is '_LC007', type is buried 
-- synthesized logic cell 
_LC007   = LCELL( _EQ014 $  GND);
  _EQ014 =  _LC009 & !_LC012 & !_LC029
         # !_LC029 & !nDREQ
         # !_LC002 & !_LC003 & !_LC004 & !_LC006 & !_LC009 & !_LC010 & 
              _LC012 & !nDmaStart
         #  _LC006 &  _LC012 &  nDREQ
         #  _LC006 &  _LC008 &  nDREQ;

-- Node name is '|DMATEST:m0|:294' 
-- Equation name is '_LC006', type is buried 
_LC006   = DFFE( _EQ015 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ015 =  _LC006 &  nDREQ
         #  _LC006 & !_LC008 & !_LC009 & !_LC012
         # !_LC008 &  _LC009 & !_LC012 &  nDREQ;

-- Node name is '|DMATEST:m0|:295' 
-- Equation name is '_LC012', type is buried 
_LC012   = DFFE( _EQ016 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ016 = !_LC006 & !_LC008 & !_LC009 &  _LC012
         # !_LC002 & !_LC003 & !_LC004 & !_LC006 &  _LC008 & !_LC010 & 
              _LC012 & !nDmaStart
         # !_LC006 &  _LC008 &  _LC009 &  _LC012
         # !dmaMode0 &  dmaMode1 & !_LC006 & !_LC008 & !_LC009 & !_LC013
         # !_LC006 &  _LC008 &  _LC009 &  _LC029;

-- Node name is '|DMATEST:m0|:296' 
-- Equation name is '_LC009', type is buried 
_LC009   = DFFE( _EQ017 $  VCC, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ017 =  _LC006 &  nDREQ
         # !_LC002 & !_LC003 & !_LC004 & !_LC009 & !_LC010 &  _LC012 &  nDREQ
         # !_LC008 & !_LC009 &  nDREQ &  _X002
         #  _LC009 & !_LC012 &  nDREQ &  _X003;
  _X002  = EXP(!dmaMode0 &  dmaMode1 & !_LC012 & !_LC013);
  _X003  = EXP( _LC008 & !_LC029);

-- Node name is '|DMATEST:m0|:297' 
-- Equation name is '_LC008', type is buried 
_LC008   = DFFE( _EQ018 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ018 =  dmaMode0 & !dmaMode1 & !_LC006 & !_LC008 & !_LC009 & !_LC013
         # !_LC006 & !_LC008 & !_LC009 &  _LC012
         # !_LC008 &  _LC009 & !_LC012 &  nDREQ
         # !_LC006 &  _LC008 &  _LC009 &  _LC012
         #  _LC007;

-- Node name is '|WAITTEST:w0|:93' = '|WAITTEST:w0|counter0' 
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE( _EQ019 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ019 =  _LC025 & !_LC027 & !_LC028
         #  _LC027 &  _LC028
         # !_LC020 & !_LC025 &  _LC027;

-- Node name is '|WAITTEST:w0|:92' = '|WAITTEST:w0|counter1' 
-- Equation name is '_LC030', type is buried 
_LC030   = DFFE( _EQ020 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ020 =  _LC028 &  _LC030
         # !_LC020 & !_LC025 &  _LC030
         #  _LC025 &  _LC027 &  _LC030
         #  _LC025 & !_LC027 & !_LC028 & !_LC030;

-- Node name is '|WAITTEST:w0|:91' = '|WAITTEST:w0|counter2' 
-- Equation name is '_LC031', type is buried 
_LC031   = DFFE( _EQ021 $  GND, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ021 =  _LC028 &  _LC031
         # !_LC020 & !_LC025 &  _LC031
         #  _LC025 &  _LC027 &  _LC031
         #  _LC025 &  _LC030 &  _LC031
         #  _LC025 & !_LC027 & !_LC028 & !_LC030 & !_LC031;

-- Node name is '|WAITTEST:w0|:90' = '|WAITTEST:w0|counter3' 
-- Equation name is '_LC032', type is buried 
_LC032   = TFFE( _EQ022, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ022 =  _LC025 & !_LC027 & !_LC028 & !_LC030 & !_LC031
         #  _LC020 & !_LC025 & !_LC028 &  _LC032;

-- Node name is '|WAITTEST:w0|:210' = '|WAITTEST:w0|wState0' 
-- Equation name is '_LC020', type is buried 
_LC020   = DFFE( _EQ023 $  _EQ024, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ023 =  _LC020 & !_LC025 & !_LC028 &  _X004 &  _X005
         # !_LC025 & !_LC028 &  nGCS4 &  _X004 &  _X005
         #  _LC019 &  _LC025 &  _LC028 &  _X004 &  _X005
         # !_LC020 &  _LC025 &  _LC028 &  _X004 &  _X005;
  _X004  = EXP( _LC020 & !_LC027 & !_LC028 & !_LC030 & !_LC031 & !_LC032);
  _X005  = EXP( _LC019 &  _LC020 & !_LC025 &  nOE);
  _EQ024 =  _X004 &  _X005;
  _X004  = EXP( _LC020 & !_LC027 & !_LC028 & !_LC030 & !_LC031 & !_LC032);
  _X005  = EXP( _LC019 &  _LC020 & !_LC025 &  nOE);

-- Node name is '|WAITTEST:w0|:209' = '|WAITTEST:w0|wState1' 
-- Equation name is '_LC025', type is buried 
_LC025   = TFFE( _EQ025, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ025 =  _LC020 & !_LC025 & !nGCS4 &  nOE
         #  _LC020 & !_LC025 & !_LC028
         # !_LC020 &  _LC025 &  _LC028 &  nGCS4
         #  _LC020 & !_LC027 & !_LC028 & !_LC030 & !_LC031 & !_LC032
         #  _LC019 &  _LC020 &  _LC025 &  _LC028;

-- Node name is '|WAITTEST:w0|:208' = '|WAITTEST:w0|wState2' 
-- Equation name is '_LC028', type is buried 
_LC028   = TFFE( _EQ026, GLOBAL( clock), GLOBAL( nReset),  VCC,  VCC);
  _EQ026 =  _LC019 &  _LC020 &  _LC028 &  nGCS4 &  nOE
         #  _LC020 &  _LC025 & !_LC027 & !_LC028 & !_LC030 & !_LC031 & 
             !_LC032
         #  _LC019 &  _LC020 &  _LC025 &  _LC028
         # !_LC020 &  _LC025 &  _LC028 &  nGCS4;

-- Node name is '|WAITTEST:w0|~239~2' 
-- Equation name is '_LC017', type is buried 
-- synthesized logic cell 
_LC017   = LCELL( _EQ027 $  GND);
  _EQ027 = !nGCS4 & !nOE;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                           c:\d\mcu\2410\altera\buf2410.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000AE' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,395K