📄 buf2410.rpt
字号:
39 - - INPUT G 0 0 0 0 0 0 0 nReset
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
34 18 B OUTPUT s t 0 0 0 2 0 0 0 BUFDIR
30 22 B OUTPUT t 0 0 0 2 0 0 0 BUFDIR1
27 24 B TRI t ! 0 0 0 0 2 0 0 data0
28 23 B TRI t 0 0 0 0 2 0 0 data1
31 21 B TRI s t ! 0 0 0 0 2 0 0 data2
33 19 B TRI t 0 0 0 0 2 0 3 data3
10 11 A OUTPUT t ! 0 0 0 0 4 0 4 nDREQ
42 1 A OUTPUT t 0 0 0 9 0 0 0 nEXTBUS
15 16 A OPNDRN t 1 0 0 1 3 0 0 nWAIT_OD
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(12) 13 A DFFE + t 0 0 0 1 0 0 3 |DMATEST:m0|snDmaStart (|DMATEST:m0|:20)
(21) 29 B DFFE + t 0 0 0 1 0 0 3 |DMATEST:m0|snDACK (|DMATEST:m0|:77)
(1) 4 A TFFE + t 0 0 0 0 8 0 4 |DMATEST:m0|counter3 (|DMATEST:m0|:202)
(43) 2 A TFFE + t 0 0 0 0 7 0 5 |DMATEST:m0|counter2 (|DMATEST:m0|:203)
(44) 3 A TFFE + t 0 0 0 0 6 0 6 |DMATEST:m0|counter1 (|DMATEST:m0|:204)
(8) 10 A DFFE + t 1 0 1 0 5 0 7 |DMATEST:m0|counter0 (|DMATEST:m0|:205)
(5) 7 A OR2 s t 1 0 1 1 10 0 1 |DMATEST:m0|~291~1
(3) 6 A DFFE + t 0 0 0 0 5 1 9 |DMATEST:m0|:294
(11) 12 A DFFE + t 1 0 1 3 10 1 9 |DMATEST:m0|:295
(7) 9 A DFFE + t 2 0 0 2 11 1 9 |DMATEST:m0|:296
(6) 8 A DFFE + t 1 0 1 2 7 1 9 |DMATEST:m0|:297
(18) 32 B TFFE + t 0 0 0 0 7 0 4 |WAITTEST:w0|counter3 (|WAITTEST:w0|:90)
(19) 31 B DFFE + t 1 0 1 0 6 0 5 |WAITTEST:w0|counter2 (|WAITTEST:w0|:91)
(20) 30 B DFFE + t 0 0 0 0 5 0 6 |WAITTEST:w0|counter1 (|WAITTEST:w0|:92)
(23) 27 B DFFE + t 0 0 0 0 4 0 7 |WAITTEST:w0|counter0 (|WAITTEST:w0|:93)
(22) 28 B TFFE + t 0 0 0 2 8 5 7 |WAITTEST:w0|wState2 (|WAITTEST:w0|:208)
(26) 25 B TFFE + t 1 0 1 2 8 5 7 |WAITTEST:w0|wState1 (|WAITTEST:w0|:209)
(32) 20 B DFFE + t 3 0 1 2 8 1 7 |WAITTEST:w0|wState0 (|WAITTEST:w0|:210)
(35) 17 B SOFT s t 0 0 0 2 0 0 0 |WAITTEST:w0|~239~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------- LC13 |DMATEST:m0|snDmaStart
| +----------------------- LC4 |DMATEST:m0|counter3
| | +--------------------- LC2 |DMATEST:m0|counter2
| | | +------------------- LC3 |DMATEST:m0|counter1
| | | | +----------------- LC10 |DMATEST:m0|counter0
| | | | | +--------------- LC7 |DMATEST:m0|~291~1
| | | | | | +------------- LC6 |DMATEST:m0|:294
| | | | | | | +----------- LC12 |DMATEST:m0|:295
| | | | | | | | +--------- LC9 |DMATEST:m0|:296
| | | | | | | | | +------- LC8 |DMATEST:m0|:297
| | | | | | | | | | +----- LC11 nDREQ
| | | | | | | | | | | +--- LC1 nEXTBUS
| | | | | | | | | | | | +- LC16 nWAIT_OD
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC13 -> - - - - - - - * * * - - - | * - | <-- |DMATEST:m0|snDmaStart
LC4 -> - * - - - * - * * - - - - | * - | <-- |DMATEST:m0|counter3
LC2 -> - * * - - * - * * - - - - | * - | <-- |DMATEST:m0|counter2
LC3 -> - * * * - * - * * - - - - | * - | <-- |DMATEST:m0|counter1
LC10 -> - * * * * * - * * - - - - | * - | <-- |DMATEST:m0|counter0
LC7 -> - - - - - - - - - * - - - | * - | <-- |DMATEST:m0|~291~1
LC6 -> - * * * * * * * * * * - - | * - | <-- |DMATEST:m0|:294
LC12 -> - * * * * * * * * * * - - | * - | <-- |DMATEST:m0|:295
LC9 -> - * * * * * * * * * * - - | * - | <-- |DMATEST:m0|:296
LC8 -> - * * * * * * * * * * - - | * - | <-- |DMATEST:m0|:297
LC11 -> - - - - - * * - * * - - - | * - | <-- nDREQ
Pin
37 -> - - - - - - - - - - - - - | - - | <-- clock
19 -> - - - - - - - * * * - - - | * - | <-- dmaMode0
18 -> - - - - - - - * * * - - - | * - | <-- dmaMode1
20 -> * - - - - * - * - - - - - | * - | <-- nDmaStart
14 -> - - - - - - - - - - - * - | * * | <-- nFRE
13 -> - - - - - - - - - - - * - | * - | <-- nFWE
43 -> - - - - - - - - - - - * - | * - | <-- nGCS0
44 -> - - - - - - - - - - - * - | * - | <-- nGCS1
2 -> - - - - - - - - - - - * - | * - | <-- nGCS2
3 -> - - - - - - - - - - - * - | * - | <-- nGCS3
5 -> - - - - - - - - - - - * * | * * | <-- nGCS4
6 -> - - - - - - - - - - - * - | * - | <-- nGCS5
8 -> - - - - - - - - - - - * - | * - | <-- nGCS6
39 -> - - - - - - - - - - - - - | - - | <-- nReset
LC29 -> - - - - - * - * * - - - - | * - | <-- |DMATEST:m0|snDACK
LC28 -> - - - - - - - - - - - - * | * * | <-- |WAITTEST:w0|wState2
LC25 -> - - - - - - - - - - - - * | * * | <-- |WAITTEST:w0|wState1
LC20 -> - - - - - - - - - - - - * | * * | <-- |WAITTEST:w0|wState0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC18 BUFDIR
| +--------------------------- LC22 BUFDIR1
| | +------------------------- LC24 data0
| | | +----------------------- LC23 data1
| | | | +--------------------- LC21 data2
| | | | | +------------------- LC19 data3
| | | | | | +----------------- LC29 |DMATEST:m0|snDACK
| | | | | | | +--------------- LC32 |WAITTEST:w0|counter3
| | | | | | | | +------------- LC31 |WAITTEST:w0|counter2
| | | | | | | | | +----------- LC30 |WAITTEST:w0|counter1
| | | | | | | | | | +--------- LC27 |WAITTEST:w0|counter0
| | | | | | | | | | | +------- LC28 |WAITTEST:w0|wState2
| | | | | | | | | | | | +----- LC25 |WAITTEST:w0|wState1
| | | | | | | | | | | | | +--- LC20 |WAITTEST:w0|wState0
| | | | | | | | | | | | | | +- LC17 |WAITTEST:w0|~239~2
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> - - - - - - - - - - - * * * - | - * | <-- data3
LC32 -> - - - - - - - * - - - * * * - | - * | <-- |WAITTEST:w0|counter3
LC31 -> - - - - - - - * * - - * * * - | - * | <-- |WAITTEST:w0|counter2
LC30 -> - - - - - - - * * * - * * * - | - * | <-- |WAITTEST:w0|counter1
LC27 -> - - - - - - - * * * * * * * - | - * | <-- |WAITTEST:w0|counter0
LC28 -> - - * * * * - * * * * * * * - | * * | <-- |WAITTEST:w0|wState2
LC25 -> - - * * * * - * * * * * * * - | * * | <-- |WAITTEST:w0|wState1
LC20 -> - - - - - - - * * * * * * * - | * * | <-- |WAITTEST:w0|wState0
Pin
37 -> - - - - - - - - - - - - - - - | - - | <-- clock
12 -> - - - - - - * - - - - - - - - | - * | <-- nDACK
14 -> * * - - - - - - - - - - - - - | * * | <-- nFRE
5 -> - - - - - - - - - - - * * * * | * * | <-- nGCS4
35 -> * * - - - - - - - - - * * * * | - * | <-- nOE
39 -> - - - - - - - - - - - - - - - | - - | <-- nReset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** EQUATIONS **
addr0 : INPUT;
addr1 : INPUT;
addr2 : INPUT;
addr3 : INPUT;
clock : INPUT;
dmaMode0 : INPUT;
dmaMode1 : INPUT;
nDACK : INPUT;
nDmaStart : INPUT;
nFCE : INPUT;
nFRE : INPUT;
nFWE : INPUT;
nGCS0 : INPUT;
nGCS1 : INPUT;
nGCS2 : INPUT;
nGCS3 : INPUT;
nGCS4 : INPUT;
nGCS5 : INPUT;
nGCS6 : INPUT;
nOE : INPUT;
nReset : INPUT;
-- Node name is 'BUFDIR' = '|BUFDIR:b1|~4~1'
-- Equation name is 'BUFDIR', type is output
BUFDIR = LCELL( _EQ001 $ GND);
_EQ001 = nFRE & nOE;
-- Node name is 'BUFDIR1' = '|BUFDIR:b1|:4'
-- Equation name is 'BUFDIR1', type is output
BUFDIR1 = LCELL( _EQ002 $ GND);
_EQ002 = nFRE & nOE;
-- Node name is 'data0' = '|WAITTEST:w0|:239'
-- Equation name is 'data0', type is output
data0 = TRI(!_LC024, _LC017);
!_LC024 = _LC024~NOT;
_LC024~NOT = LCELL( _EQ003 $ GND);
_EQ003 = !_LC028
# _LC025;
-- Node name is 'data1' = '|WAITTEST:w0|:247'
-- Equation name is 'data1', type is output
data1 = TRI(_LC023, _LC017);
_LC023 = LCELL( _EQ004 $ GND);
_EQ004 = !_LC025 & _LC028;
-- Node name is 'data2' = '|WAITTEST:w0|~239~1'
-- Equation name is 'data2', type is output
data2 = TRI(!_LC021, _LC017);
!_LC021 = _LC021~NOT;
_LC021~NOT = LCELL( _EQ005 $ GND);
_EQ005 = !_LC028
# _LC025;
-- Node name is 'data3' = '|WAITTEST:w0|:245'
-- Equation name is 'data3', type is output
data3 = TRI(_LC019, _LC017);
_LC019 = LCELL( _EQ006 $ GND);
_EQ006 = !_LC025 & _LC028;
-- Node name is 'nDREQ' = '|DMATEST:m0|:70'
-- Equation name is 'nDREQ', type is output
nDREQ = _LC011~NOT;
_LC011~NOT = LCELL( _EQ007 $ GND);
_EQ007 = _LC006
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