📄 buf2410.rpt
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Project Information c:\d\mcu\2410\altera\buf2410.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/03/2002 15:12:16
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
buf2410 EPM7032AETC44-4 21 9 0 28 5 87 %
User Pins: 21 9 0
Project Information c:\d\mcu\2410\altera\buf2410.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop '|DMATEST:m0|:293' stuck at GND
Info: Reserved unused input pin 'nFCE' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'addr3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'addr2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'addr1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'addr0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information c:\d\mcu\2410\altera\buf2410.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clock' chosen for auto global Clock
INFO: Signal 'nReset' chosen for auto global Clear
Project Information c:\d\mcu\2410\altera\buf2410.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
buf2410@21 addr0
buf2410@22 addr1
buf2410@23 addr2
buf2410@25 addr3
buf2410@34 BUFDIR
buf2410@30 BUFDIR1
buf2410@37 clock
buf2410@27 data0
buf2410@28 data1
buf2410@31 data2
buf2410@33 data3
buf2410@19 dmaMode0
buf2410@18 dmaMode1
buf2410@12 nDACK
buf2410@20 nDmaStart
buf2410@10 nDREQ
buf2410@42 nEXTBUS
buf2410@11 nFCE
buf2410@14 nFRE
buf2410@13 nFWE
buf2410@43 nGCS0
buf2410@44 nGCS1
buf2410@2 nGCS2
buf2410@3 nGCS3
buf2410@5 nGCS4
buf2410@6 nGCS5
buf2410@8 nGCS6
buf2410@35 nOE
buf2410@39 nReset
buf2410@15 nWAIT_OD
Project Information c:\d\mcu\2410\altera\buf2410.rpt
** FILE HIERARCHY **
|bufctrl:b0|
|bufdir:b1|
|dmatest:m0|
|dmatest:m0|lpm_add_sub:308|
|dmatest:m0|lpm_add_sub:308|addcore:adder|
|dmatest:m0|lpm_add_sub:308|addcore:adder|addcore:adder0|
|dmatest:m0|lpm_add_sub:308|altshift:result_ext_latency_ffs|
|dmatest:m0|lpm_add_sub:308|altshift:carry_ext_latency_ffs|
|dmatest:m0|lpm_add_sub:308|altshift:oflow_ext_latency_ffs|
|waittest:w0|
|waittest:w0|lpm_add_sub:249|
|waittest:w0|lpm_add_sub:249|addcore:adder|
|waittest:w0|lpm_add_sub:249|addcore:adder|addcore:adder0|
|waittest:w0|lpm_add_sub:249|altshift:result_ext_latency_ffs|
|waittest:w0|lpm_add_sub:249|altshift:carry_ext_latency_ffs|
|waittest:w0|lpm_add_sub:249|altshift:oflow_ext_latency_ffs|
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
***** Logic for device 'buf2410' compiled without errors.
Device: EPM7032AETC44-4
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** ERROR SUMMARY **
Info: Chip 'buf2410' in device 'EPM7032AETC44-4' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
n
E V n B
n n X C R c U
G G T C e l F
C C B I G s G o G n D
S S U N N e N c N O I
1 0 S T D t D k D E R
-----------------------------------_
/ 44 43 42 41 40 39 38 37 36 35 34 |
#TDI | 1 33 | data3
nGCS2 | 2 32 | #TDO
nGCS3 | 3 31 | data2
GND | 4 30 | BUFDIR1
nGCS4 | 5 29 | VCCIO
nGCS5 | 6 EPM7032AETC44-4 28 | data1
#TMS | 7 27 | data0
nGCS6 | 8 26 | #TCK
VCCIO | 9 25 | addr3
nDREQ | 10 24 | GND
nFCE | 11 23 | addr2
|_ 12 13 14 15 16 17 18 19 20 21 22 _|
------------------------------------
n n n n G V d d n a a
D F F W N C m m D d d
A W R A D C a a m d d
C E E I I M M a r r
K T N o o S 0 1
_ T d d t
O e e a
D 1 0 r
t
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 13/16( 81%) 16/16(100%) 7/16( 43%) 27/36( 75%)
B: LC17 - LC32 15/16( 93%) 16/16(100%) 5/16( 31%) 12/36( 33%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 28/32 ( 87%)
Total shareable expanders used: 5/32 ( 15%)
Total Turbo logic cells used: 28/32 ( 87%)
Total shareable expanders not available (n/a): 7/32 ( 21%)
Average fan-in: 7.07
Total fan-in: 198
Total input pins required: 21
Total fast input logic cells required: 0
Total output pins required: 9
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 28
Total flipflops required: 17
Total product terms required: 86
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 5
Synthesized logic cells: 4/ 32 ( 12%)
Device-Specific Information: c:\d\mcu\2410\altera\buf2410.rpt
buf2410
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
21 (29) (B) INPUT 0 0 0 0 0 0 0 addr0
22 (28) (B) INPUT 0 0 0 0 0 0 0 addr1
23 (27) (B) INPUT 0 0 0 0 0 0 0 addr2
25 (26) (B) INPUT 0 0 0 0 0 0 0 addr3
37 - - INPUT G 0 0 0 0 0 0 0 clock
19 (31) (B) INPUT 0 0 0 0 0 0 3 dmaMode0
18 (32) (B) INPUT 0 0 0 0 0 0 3 dmaMode1
12 (13) (A) INPUT 0 0 0 0 0 0 1 nDACK
20 (30) (B) INPUT 0 0 0 0 0 0 3 nDmaStart
11 (12) (A) INPUT 0 0 0 0 0 0 0 nFCE
14 (15) (A) INPUT 0 0 0 0 0 3 0 nFRE
13 (14) (A) INPUT 0 0 0 0 0 1 0 nFWE
43 (2) (A) INPUT 0 0 0 0 0 1 0 nGCS0
44 (3) (A) INPUT 0 0 0 0 0 1 0 nGCS1
2 (5) (A) INPUT 0 0 0 0 0 1 0 nGCS2
3 (6) (A) INPUT 0 0 0 0 0 1 0 nGCS3
5 (7) (A) INPUT 0 0 0 0 0 2 4 nGCS4
6 (8) (A) INPUT 0 0 0 0 0 1 0 nGCS5
8 (10) (A) INPUT 0 0 0 0 0 1 0 nGCS6
35 (17) (B) INPUT 0 0 0 0 0 2 4 nOE
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