usbinit.c

How to control USB interface under SZ platform

// This routine is called by the device manager during installation stage.

#include "usb_pptt.h"
#include "usb_pdef.h"
#include "hal_pptt.h"

void _iUsbDelay(U32 count);
void _iUsbLoadEPconfig(void);
void _iUsbReset(void);

U8      _gUsbMode;          // operation mode of driver
U8      _gUsbDrvStatus[2];  // Drive status

/* constants for configuration of USB device module */
const U32 _gUsbEPnSTATsetting[5] = {
    0x02,   /* EP0: 8 bytes/control/flush FIFO */
    0x1A,   /* EP1: out/8 bytes/intr/flush FIFO */
    0x9A,   /* EP2: in/8 bytes/intr/flush FIFO */
    0x72,   /* EP3: out/64 bytes/bulk/flush FIFO */
    0xF2    /* EP4: in/64 bytes/bulk/flush FIFO */
    };
    
const U32 _gUsbEPnFCTRLsetting[5] = {
//    0x08000000, /*  EP0:FRAME on / GR[2:0]=000 */
    0x08000000, /*  EP0:FRAME on / GR[2:0]=111 */
    0x08000000, /*  EP1:FRAME on / GR[2:0]=011 */
    0x08000000, /*  EP2:FRAME on / GR[2:0]=011 */
    0x0F000000, /*  EP3:FRAME on / GR[2:0]=000 */
    0x08000000  /*  EP4:FRAME on / GR[2:0]=000 */
    };
    
const U32 _gUsbEPnFALRMsetting[5] = {
//    0x00,   /*  EP0:ALRM[6:0]=0x00 */
    0x00,   /*  EP0:ALRM[6:0]=0x10 */
    0x00,   /*  EP1:ALRM[6:0]=0x08 */
    0x00,   /*  EP2:ALRM[6:0]=0x08 */
    0x20,   /*  EP3:ALRM[6:0]=0x40 */
    0x00    /*  EP4:ALRM[6:0]=0x40 */
    };
    
const U32 _gUsbUDCepConfData[25] = {
    /* EP0: 0b0000 0000 000 00 0 0000001000 00 00000000000 000
           =0b0000 0000 0000 0000 0000 1000 0000 0000 0000 0000
           =0x00 00 08 00 00 */
    0x00,
    0x00,
    0x08,
    0x00,
    0x00,
    /* EP1: 0b0001 0100 000 11 0 0000001000 11 00000000000 001
           =0b0001 0100 0001 1000 0000 1000 1100 0000 0000 0001
           =0x14 18 08 C0 01 */
    0x14,
    0x18,
    0x08,
    0xC0,
    0x01,
    /* EP2: 0b0010 0100 000 11 1 0000001000 11 00000000000 010
           =0b0010 0100 0001 1100 0000 1000 1100 0000 0000 0010
           =0x24 14 08 C0 02 */
    0x24,
    0x1C,
    0x08,
    0xC0,
    0x02,
    /* EP3: 0b0011 0100 000 10 0 0001000000 11 00000000000 011
           =0b0011 0100 0001 0000 0100 0000 1100 0000 0000 0011
           =0x34 10 40 C0 03 */
    0x34,
    0x10,
    0x40,
    0xC0,
    0x03,
    /* EP4: 0b0100 0100 000 10 1 0001000000 11 00000000000 100
           =0b0100 0100 0001 0100 0100 0000 1100 0000 0000 0100
           =0x44 14 40 C0 04 */
    0x44,
    0x14,
    0x40,
    0xC0,
    0x04
    };

// The following registers are used for USB pin, clock and interrupt set up
#define _reg_PLLCR      (*(volatile U16 *) (0xFFFFF200))
#define _reg_MPFSR0     (*(volatile U16 *) (0xFFFFF202))
#define _reg_MPFSR1     (*(volatile U16 *) (0xFFFFF204))
#define _reg_UPFSR0     (*(volatile U16 *) (0xFFFFF208))
#define _reg_UPFSR1     (*(volatile U16 *) (0xFFFFF20A))
#define _reg_CSCR       (*(volatile U16 *) (0xFFFFF20C))
#define _reg_PNPUEN     (*(volatile U8 *)  (0xFFFFF452))
#define _reg_PNSEL      (*(volatile U8 *)  (0xFFFFF453))
#define _reg_IMR        (*(volatile U32 *) (0xFFFFF304))
#define USBD_INTR_MASK  0x80000000
            
// return SYS_OK always
STATUS _UsbInit(void)
{
	TEXT    taskName[] = { 'U', 'S', 'B', '_', 'R', 'W', '\0' };
    
    // config port to USBD, instead of I/O
    _reg_PNSEL = 0;
    _reg_PNPUEN = 0;    // no pull up is needed

    // config USB clock to 48 MHz
    // use the 16M crystal generated 16M clock as source
/*    
    _reg_UPFSR0 = 0x3400;
    _reg_UPFSR1 = 0x0000;
    _reg_PLLCR = 0x6400;
    _reg_CSCR = 0xcc0c;
*/        
        
    // use the 32.768K crystal generated 16M clock as source
    _reg_UPFSR0 = 0x2969;
    _reg_UPFSR1 = 0x01f3;
    _reg_PLLCR = 0x6400;    
    _reg_CSCR = 0x4C0C;     

        
    // enable USB device interrupt 
    _reg_IMR &= (~USBD_INTR_MASK);
    
    /* initialize variables */
    _gUsbDrvStatus[0] = _gUsbDrvStatus[1] = USB_DRV_NOT_READY;  

    /* register interrupt handler */
    _HalAttachIsr(USB_INTR_SOURCE, (P_VOID)_UsbIntrHandler);

    _iUsbReset();
    	
	return SYS_OK;
}

void _iUsbDelay(U32 count)
{
    U32 i;
    
    i = 0;
    while (i<count)
    {
        i++;
    }        
}

void _iUsbLoadEPconfig()
{
	U32		i,j;
	
	for (i=0; i<25; i++)		/* there are 25 bytes of config data */
	{
		_reg_USB_DDAT = _gUsbUDCepConfData[i];
		while(_reg_USB_CFGSTAT & 0x40000000);	/* wait until BSY bit cleared */
	}
	/* wait until CFG bit is cleared */
	while (_reg_USB_CFGSTAT & 0x80000000);	
}

void _iUsbReset()
{
	/* reset and enable USB device module */
	_reg_USB_ENAB = 0x00000000;	    /* disable module */
	_iUsbDelay(10);
	_reg_USB_ENAB = 0x80000000;	    /* enable and reset module */
	/* remark: resetting the module will enable module automatically */
	while (_reg_USB_ENAB & 0x80000000);	    /* wait until reset cleared */
	
	/* load configuration information to endpoint buffer */
	_iUsbLoadEPconfig();
	
	/* setup module level interrupts */
	_reg_USB_GEN_ISR = 0x800000FF;	    /* clear all interrupts */
	_reg_USB_MASK = 0x800000FF;	        /* mask all interrupts */
	
	/*** setup endpoint registers ***/
	/* clear interrupts of endpoints */
	_reg_USB_EP0_ISR = 0x000001FF;
	_reg_USB_EP1_ISR = 0x000001FF;
	_reg_USB_EP2_ISR = 0x000001FF;
	_reg_USB_EP3_ISR = 0x000001FF;
	_reg_USB_EP4_ISR = 0x000001FF;
	/* mask all interrupts */
	_reg_USB_EP0_MASK = 0x000001FF;
	_reg_USB_EP1_MASK = 0x000001FF;
	_reg_USB_EP2_MASK = 0x000001FF;
	_reg_USB_EP3_MASK = 0x000001FF;
	_reg_USB_EP4_MASK = 0x000001FF;
	/* configure USB_EPn_STAT registers and flush FIFOs */
	_reg_USB_EP0_STAT = _gUsbEPnSTATsetting[0];
	_reg_USB_EP1_STAT = _gUsbEPnSTATsetting[1];
	_reg_USB_EP2_STAT = _gUsbEPnSTATsetting[2];
	_reg_USB_EP3_STAT = _gUsbEPnSTATsetting[3];
	_reg_USB_EP4_STAT = _gUsbEPnSTATsetting[4];
	/* configure USB_EPn_FCTRL registers */
	_reg_USB_EP0_FCTRL = _gUsbEPnFCTRLsetting[0];
	_reg_USB_EP1_FCTRL = _gUsbEPnFCTRLsetting[1];
	_reg_USB_EP2_FCTRL = _gUsbEPnFCTRLsetting[2];
	_reg_USB_EP3_FCTRL = _gUsbEPnFCTRLsetting[3];
	_reg_USB_EP4_FCTRL = _gUsbEPnFCTRLsetting[4];
	/* configure USB_EPn_FALRM registers */
	_reg_USB_EP0_FALRM = _gUsbEPnFALRMsetting[0];
	_reg_USB_EP1_FALRM = _gUsbEPnFALRMsetting[1];
	_reg_USB_EP2_FALRM = _gUsbEPnFALRMsetting[2];
	_reg_USB_EP3_FALRM = _gUsbEPnFALRMsetting[3];
	_reg_USB_EP4_FALRM = _gUsbEPnFALRMsetting[4];
    
    /* enable DEVREQ interrupt for endpoint 0 */
//    _reg_USB_EP0_MASK = (ENABLE_DEVREQ & ENABLE_EOT & ENABLE_EOF);
    _reg_USB_EP0_MASK = ENABLE_DEVREQ;
    
    /* enable EOT interrupt for endpoint 3, for command */
    _reg_USB_EP3_MASK = ENABLE_EOT & ENABLE_EOF;
//    _reg_USB_EP3_MASK = ENABLE_EOT;

    /* enable EOF interrupt for endpoint 4, for data to host */
    _reg_USB_EP4_MASK = ENABLE_EOF; // enable EOF interrupt

    // enable configuration change interrupt
    _reg_USB_MASK = ENABLE_CFG_CHG & ENABLE_RESET & ENABLE_SOF;
    
	/* enable USB device module */
	_reg_USB_CTRL = 0x0000001A;
}