usb_pdef.h

How to control USB interface under SZ platform

#ifndef USB_P_DEF_INC
#define USB_P_DEF_INC

#include "os_def.h"
#include "dma_def.h"

// constant for last sector from host handling
#define LAST_SECT_PENDING       1
#define LAST_SECT_DONE          2

/* error code definition */
#define ERR_USB_NO_SUPPORT      0x1A00

/* constant definition */
#define NO_DMA_CH               0xFF    /* value returned from API _DmaRequestChannel
                                           when no DMA channel is availiable */
#define ENABLE_EOT              0x1FB   /* enable EOT interrupt for a particular endpoint */
#define ENABLE_DEVREQ           0x1FD   /* enable DEVREQ interrupt for a particular endpoint */
#define ENABLE_EOF              0x1FE   /* enable EOF interrupt for a particular endpoint */
#define DISABLE_ALL             0x1FF   /* disable all interrupts for a particular endpoint */
#define ENABLE_CFG_CHG          0x800000FE  // enable configuration change interrupt
#define ENABLE_RESET            0x800000EF  // enable USB bus reset interrupt
#define ENABLE_SOF              0x800000BF  // enable SOF interrupt

/* device mode definition */
#define USB_USE_INTR_ONLY       0
#define USB_USE_DMA             1

// device status definition
#define USB_DRV_NOT_READY       0
#define USB_DRV_READY           1

/* interrupt source definition */
#define USB_INTR_SOURCE         31

/* DMA source definition */
#define USB_DMA_SOURCE_EP0      25
#define USB_DMA_SOURCE_EP1      26
#define USB_DMA_SOURCE_EP2      27
#define USB_DMA_SOURCE_EP3      16  
#define USB_DMA_SOURCE_EP4      17

/* USB interrupt status register bit mask definition */
#define USB_INTR_GEN_MASK       0x00000020  // general interrupt
#define USB_INTR_EP4_MASK       0x00000010  // interrupt from EP4
#define USB_INTR_EP3_MASK       0x00000008  // interrupt from EP3
#define USB_INTR_EP2_MASK       0x00000004  // interrupt from EP2
#define USB_INTR_EP1_MASK       0x00000002  // interrupt from EP1
#define USB_INTR_EP0_MASK       0x00000001  // interrupt from EP0

/* USB endpoint interrupt status bit mask definition */
#define USB_CFG_CHG_MASK        0x00000001  // CFG_CHG interrupt
#define USB_RESET_MASK          0x00000010  // RESET_START interrupt  
#define USB_SOF_MASK            0x00000040  // SOF interrupt  
#define USB_EPINTR_EOT_MASK     0x00000004  // EOT interrupt
#define USB_EPINTR_DEVREQ_MASK  0x00000002  // DEVREQ interrupt
#define USB_EPINTR_EOF_MASK     0x00000001  // EOF interrupt

/* Command over bit mask for USB Control register */
#define USB_CTRL_CMOV_MASK      0x40

/* Zero Length Packet bit mask for endpoint status/control register */
#define USB_ZLPS_MASK           4

/*** USB device module register definition ***/   
/* module wide registers */
#define  USB_BASE       		0xFFFE0400
#define  _reg_USB_FRAME         (*(volatile U32 *) (USB_BASE+0x000))
#define  _reg_USB_SPEC       	(*(volatile U32 *) (USB_BASE+0x004))
#define  _reg_USB_STAT       	(*(volatile U32 *) (USB_BASE+0x008))
#define  _reg_USB_CTRL       	(*(volatile U32 *) (USB_BASE+0x00C))
#define  _reg_USB_CFGSTAT      	(*(volatile U32 *) (USB_BASE+0x010))
#define  _reg_USB_DDAT       	(*(volatile U32 *) (USB_BASE+0x014))
#define  _reg_USB_GEN_ISR      	(*(volatile U32 *) (USB_BASE+0x018))
#define  _reg_USB_MASK       	(*(volatile U32 *) (USB_BASE+0x01C))
#define  _reg_USB_ENAB       	(*(volatile U32 *) (USB_BASE+0x024))
#define  _reg_USB_ISR       	(*(volatile U32 *) (USB_BASE+0x028))

/* registers for end point 0 */
#define  _reg_USB_EP0_STAT   	(*(volatile U32 *) (USB_BASE+0x030))
#define  _reg_USB_EP0_ISR   	(*(volatile U32 *) (USB_BASE+0x034))
#define  _reg_USB_EP0_MASK   	(*(volatile U32 *) (USB_BASE+0x038))
#define  _reg_USB_EP0_FDAT   	(*(volatile U16 *) (USB_BASE+0x03C))
#define  _reg_USB_EP0_FSTAT  	(*(volatile U32 *) (USB_BASE+0x040))
#define  _reg_USB_EP0_FCTRL  	(*(volatile U32 *) (USB_BASE+0x044))
#define  _reg_USB_EP0_LRFP   	(*(volatile U32 *) (USB_BASE+0x048))
#define  _reg_USB_EP0_LWFP   	(*(volatile U32 *) (USB_BASE+0x04C))
#define  _reg_USB_EP0_FALRM  	(*(volatile U32 *) (USB_BASE+0x050))
#define  _reg_USB_EP0_FRDP   	(*(volatile U32 *) (USB_BASE+0x054))
#define  _reg_USB_EP0_FWRP   	(*(volatile U32 *) (USB_BASE+0x058))

/* registers for end point 1 */
#define  _reg_USB_EP1_STAT   	(*(volatile U32 *) (USB_BASE+0x060))
#define  _reg_USB_EP1_ISR   	(*(volatile U32 *) (USB_BASE+0x064))
#define  _reg_USB_EP1_MASK   	(*(volatile U32 *) (USB_BASE+0x068))
#define  _reg_USB_EP1_FDAT   	(*(volatile U16 *) (USB_BASE+0x06C))
#define  _reg_USB_EP1_FSTAT  	(*(volatile U32 *) (USB_BASE+0x070))
#define  _reg_USB_EP1_FCTRL  	(*(volatile U32 *) (USB_BASE+0x074))
#define  _reg_USB_EP1_LRFP   	(*(volatile U32 *) (USB_BASE+0x078))
#define  _reg_USB_EP1_LWFP   	(*(volatile U32 *) (USB_BASE+0x07C))
#define  _reg_USB_EP1_FALRM  	(*(volatile U32 *) (USB_BASE+0x080))
#define  _reg_USB_EP1_FRDP   	(*(volatile U32 *) (USB_BASE+0x084))
#define  _reg_USB_EP1_FWRP   	(*(volatile U32 *) (USB_BASE+0x088))

/* registers for end point 2 */
#define  _reg_USB_EP2_STAT   	(*(volatile U32 *) (USB_BASE+0x090))
#define  _reg_USB_EP2_ISR   	(*(volatile U32 *) (USB_BASE+0x094))
#define  _reg_USB_EP2_MASK   	(*(volatile U32 *) (USB_BASE+0x098))
#define  _reg_USB_EP2_FDAT   	(*(volatile U16 *) (USB_BASE+0x09C))
#define  _reg_USB_EP2_FSTAT  	(*(volatile U32 *) (USB_BASE+0x0A0))
#define  _reg_USB_EP2_FCTRL  	(*(volatile U32 *) (USB_BASE+0x0A4))
#define  _reg_USB_EP2_LRFP   	(*(volatile U32 *) (USB_BASE+0x0A8))
#define  _reg_USB_EP2_LWFP   	(*(volatile U32 *) (USB_BASE+0x0AC))
#define  _reg_USB_EP2_FALRM  	(*(volatile U32 *) (USB_BASE+0x0B0))
#define  _reg_USB_EP2_FRDP   	(*(volatile U32 *) (USB_BASE+0x0B4))
#define  _reg_USB_EP2_FWRP   	(*(volatile U32 *) (USB_BASE+0x0B8))

/* registers for end point 3 */
#define  _reg_USB_EP3_STAT   	(*(volatile U32 *) (USB_BASE+0x0C0))
#define  _reg_USB_EP3_ISR   	(*(volatile U32 *) (USB_BASE+0x0C4))
#define  _reg_USB_EP3_MASK   	(*(volatile U32 *) (USB_BASE+0x0C8))
#define  _reg_USB_EP3_FDAT   	(*(volatile U16 *) (USB_BASE+0x0CC))
#define  _reg_USB_EP3_FSTAT  	(*(volatile U32 *) (USB_BASE+0x0D0))
#define  _reg_USB_EP3_FCTRL  	(*(volatile U32 *) (USB_BASE+0x0D4))
#define  _reg_USB_EP3_LRFP   	(*(volatile U32 *) (USB_BASE+0x0D8))
#define  _reg_USB_EP3_LWFP   	(*(volatile U32 *) (USB_BASE+0x0DC))
#define  _reg_USB_EP3_FALRM  	(*(volatile U32 *) (USB_BASE+0x0E0))
#define  _reg_USB_EP3_FRDP   	(*(volatile U32 *) (USB_BASE+0x0E4))
#define  _reg_USB_EP3_FWRP   	(*(volatile U32 *) (USB_BASE+0x0E8))

/* registers for end point 4 */
#define  _reg_USB_EP4_STAT   	(*(volatile U32 *) (USB_BASE+0x0F0))
#define  _reg_USB_EP4_ISR   	(*(volatile U32 *) (USB_BASE+0x0F4))
#define  _reg_USB_EP4_MASK   	(*(volatile U32 *) (USB_BASE+0x0F8))
#define  _reg_USB_EP4_FDAT   	(*(volatile U16 *) (USB_BASE+0x0FC))
#define  _reg_USB_EP4_FSTAT  	(*(volatile U32 *) (USB_BASE+0x100))
#define  _reg_USB_EP4_FCTRL  	(*(volatile U32 *) (USB_BASE+0x104))
#define  _reg_USB_EP4_LRFP   	(*(volatile U32 *) (USB_BASE+0x108))
#define  _reg_USB_EP4_LWFP   	(*(volatile U32 *) (USB_BASE+0x10C))
#define  _reg_USB_EP4_FALRM  	(*(volatile U32 *) (USB_BASE+0x110))
#define  _reg_USB_EP4_FRDP   	(*(volatile U32 *) (USB_BASE+0x114))
#define  _reg_USB_EP4_FWRP   	(*(volatile U32 *) (USB_BASE+0x118))	

#endif