sysinit.c

How to detect Battery voltage in DragonBall SZ platform

// Last modified: Nov 19, 2001
// Template v0.4 for DBMX1
// Rev history: 
//     v0.4:
//     	 - ClockInit function now takes parameter for selecting
//         different clock speed
//		 - Added a few other init functions.
//     v0.3:
//       - Adding the AIPIInit function to initialize the AIPI
//         registers as per suggestion from designer


#define SYS_DEFINE_GLOBALS

#include <stdio.h>
#include "Common.h"
#include "MX1_def.h"
#include "ProtoType.h"

extern void SetIntType(U32 IntNum, U8 type);
extern void SetAsynchMode(void);
extern void EnableICache (void);

/////////////////////////////////////////////////
//											   //	
//	Call by user program for interupt enable   //
//											   //
/////////////////////////////////////////////////
void IrptInit(void)
{
	U32 i;
	*(P_U32)AITC_INTCNTL &= 0x00;
	/* To set all interrupt source to normal interrupt source */	
	for (i=0; i<=63; i++)
	{
		SetIntType(i, 0);
	}	 

	/* Enable all int sources */
/*	for (i=0; i<=31; i++)
	{
		EnableIntSource(i);
	}
*/
}

void AIPIInit(void)
{
	// Reset values of the AIPI registers do not match the design.
	// The design intended values are manually restored here.
	
	*(P_U32) AIPI1_PSR0 = 0xFFFFFC00;
	*(P_U32) AIPI1_PSR1 = 0xFFFFFFFF;
	*(P_U32) AIPI1_PAR = 0xFFFFFFFF;
	*(P_U32) AIPI2_PSR0 = 0xFFFFE410;
	*(P_U32) AIPI2_PSR1 = 0xFFFFFBEF;
	*(P_U32) AIPI2_PAR = 0xFFFFFFFF;
}

void ClockInit(U8 clock)
{
	switch(clock)
		{
			case 8:
				// BCLK = 8MHz setting & select BCLK at CLKO pin
				*(P_U32) CRM_CSCR = 0x2F00AC03;
				return;
			case 16: 
				// BCLK = 16MHz setting & select BCLK at CLKO pin
				*(P_U32) CRM_CSCR = 0x2F009403;
				return;
			case 24:	
				// BCLK = 24MHz setting & select BCLK at CLKO pin
				*(P_U32) CRM_CSCR = 0x2F008C03;
				return;
			case 32:	
				// BCLK = 32MHz setting & select BCLK at CLKO pin
				*(P_U32) CRM_CSCR = 0x2F008803;
				return;
			case 48:
				// BCLK = 48MHz setting & select BCLK at CLKO pin
				*(P_U32) CRM_CSCR = 0x2F008403;
				return;
			case 96:
				// BCLK = 96MHz setting & select BCLK at CLKO pin
				*(P_U32)CRM_CSCR = 0x2F008003;
				return;
			case 150:
				// Change FCLK (CPUCLK) to 150MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=1, MFD=99, MFI=9, MFN=16 
				*(P_U32)CRM_MPCTL0 = 0x04632410;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;
			case 200:
				// Change FCLK (CPUCLK) to 200MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=0, MFD=99, MFI=6, MFN=10 
				*(P_U32)CRM_MPCTL0 = 0x0063180A;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;
			case 225:
				// Change FCLK (CPUCLK) to 225MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=0, MFD=99, MFI=6, MFN=87 
				*(P_U32)CRM_MPCTL0 = 0x00631857;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;
								
			case 250:
				// Change FCLK (CPUCLK) to 250MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=0, MFD=99, MFI=7, MFN=63 
				*(P_U32)CRM_MPCTL0 = 0x00631C3F;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;
			case 275:
				// Change FCLK (CPUCLK) to 275MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=0, MFD=99, MFI=8, MFN=10 
				*(P_U32)CRM_MPCTL0 = 0x00632027;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;				
			case 300:
				// Change FCLK (CPUCLK) to 300MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=0, MFD=99, MFI=9, MFN=16 
				*(P_U32)CRM_MPCTL0 = 0x00632410;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;										
			case 350:
				// Change FCLK (CPUCLK) to 350MHz
				*(P_U32)CRM_CSCR = 0xAF008003;
				// Set PD=0, MFD=99, MFI=10, MFN=68 
				*(P_U32)CRM_MPCTL0 = 0x00632844;
				// Trigger the restart bit(bit 21) 	
				*(P_U32)CRM_CSCR |= 0x00200000;	
				// Program PRESC bit(bit 15) to 0 to divide-by-1 
				*(P_U32)CRM_CSCR &= 0xFFFF7FFF;
				SetAsynchMode();
				return;										
			default://96MHz
				// BCLK = 96MHz setting & select BCLK at CLKO pin
				*(P_U32)CRM_CSCR = 0x2F008003;
				return;				
		}					
}

void PortInit(void)
{
//clear PORT D for LCD signal
	*(P_U32)PTD_GIUS = 0x00000000;
    *(P_U32)PTD_GPR  = 0x00000000;
//config PC16 for LCD on/off
    *(P_U32)PTC_GIUS |= 0x00010000;
    *(P_U32)PTC_OCR2 |= 0x00000003;
    *(P_U32)PTC_DDIR |= 0x00010000;
    *(P_U32)PTC_GPR  |= 0x00010000;
    *(P_U32)PTC_DR   |= 0x00010000;
}

void MemInit(void)
{
	// CS0 - boot flash, 32 wait states, 8-bit ###
	*(P_U32)EIM_CS0H = 0x00002000;
	*(P_U32)EIM_CS0L = 0x11110301;
}

void ASPInit(void)
{
}

void LCDCInit(void)
{
}

void MMCInit(void)
{
}

void DSPAInit(void)
{
}

void PWMInit(void)
{
}

void SysInit(void)
{
	EnableICache();
	PortInit();
	MemInit();
	IrptInit();	
	AIPIInit();
	ASPInit();
	LCDCInit();
	MMCInit();
	DSPAInit();
	PWMInit();	
	ClockInit(200);
}