chandle.c

How to detect Battery voltage in DragonBall SZ platform

    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000200;		// clear the bit in the force reg.
}

void   fast_scr08_isr(void)	// fast_scr08_isr  (8)
{
    if((FIPNDL & 0x00000100) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000100;		// clear the bit in the force reg.
    gFastInt8flag = 1;
}

void   fast_scr40_isr(void)	// fast_scr40_isr (40)
{
    if((FIPNDH & 0x00000100) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000100;		// clear the bit in the force reg.
}

void   fast_scr07_isr(void)	// fast_scr07_isr  (7)
{
    if((FIPNDL & 0x0000080) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x0000080;		// clear the bit in the force reg.
}

void   fast_scr39_isr(void)	// fast_scr39_isr (39)
{
    if((FIPNDH & 0x00000080) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000080;		// clear the bit in the force reg.
}

void   fast_scr06_isr(void)	// fast_scr06_isr  (6)
{
    if((FIPNDL & 0x00000040) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000040;		// clear the bit in the force reg.
}

void   fast_scr38_isr(void)	// fast_scr38_isr (38)
{
    if((FIPNDH & 0x00000040) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000040;		// clear the bit in the force reg.
}

void   fast_scr05_isr(void)	// fast_scr05_isr  (5)
{
    if((FIPNDL & 0x00000020) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000020;		// clear the bit in the force reg.
}

void   fast_scr37_isr(void)	// fast_scr37_isr (37)
{
    if((FIPNDH & 0x00000020) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000020;		// clear the bit in the force reg.
}

void   fast_scr04_isr(void)	// fast_scr04_isr  (4)
{
    if((FIPNDL & 0x00000010) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000010;		// clear the bit in the force reg.
    gFastInt4flag = 1;

}

void   fast_scr36_isr(void)	// fast_scr36_isr (36)
{
    if((FIPNDH & 0x00000010) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000010;		// clear the bit in the force reg.
}

void   fast_scr03_isr(void)	// fast_scr03_isr  (3)
{
	if((FIPNDL & 0x00000008) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000008;		// clear the bit in the force reg.
}

void   fast_scr35_isr(void)	// fast_scr35_isr (35)
{
    if((FIPNDH & 0x00000008) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000008;		// clear the bit in the force reg.
}

void   fast_scr02_isr(void)	// fast_scr02_isr  (2)
{
    if((FIPNDL & 0x00000004) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000004;		// clear the bit in the force reg.
    gFastInt2flag = 1;
}

void   fast_scr34_isr(void)	// fast_scr34_isr (34)
{
    if((FIPNDH & 0x00000004) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000004;		// clear the bit in the force reg.
}

void   fast_scr01_isr(void)	// fast_scr01_isr  (1)
{
    if((FIPNDL & 0x00000002) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000002;		// clear the bit in the force reg.
    gFastInt1flag = 1;
}

void   fast_scr33_isr(void)	// fast_scr33_isr (33)
{
    if((FIPNDH & 0x00000002) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000002;		// clear the bit in the force reg.
}


void   fast_scr32_isr(void)	// fast_scr32_isr (32)
{
    if((FIPNDH & 0x00000001) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000001;		// clear the bit in the force reg.
    gFastInt32flag = 1;
}

void   fast_scr00_isr(void)	// fast_scr00_isr  (0)
{
    if((FIPNDL & 0x00000001) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000001;		// clear the bit in the force reg.
    gFastInt0flag = 1;
}

/*************************/
/* Normal Interrupt ISRs */
/*************************/

void   norm_scr63_isr(void)	// norm_scr63_isr (63)
{
    if((NIPNDH & 0x80000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>28)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x80000000;		// clear the bit in the force reg.
    gNormInt63flag = 1;

}

void   norm_scr62_isr(void)	// norm_scr62_isr (62)
{
    if((NIPNDH & 0x40000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>24)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x40000000;		// clear the bit in the force reg.
    gNormInt62flag = 1;

}

void   norm_scr61_isr(void)	// norm_scr61_isr (61)
{
    if((NIPNDH & 0x20000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>20)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x20000000;		// clear the bit in the force reg.
    gNormInt61flag = 1;

}

void   norm_scr60_isr(void)	// norm_scr60_isr (60)
{
    if((NIPNDH & 0x10000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>16)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x10000000;		// clear the bit in the force reg.

}

void   norm_scr59_isr(void)	// norm_scr59_isr (59)
{
    if((NIPNDH & 0x08000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>12)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x08000000;		// clear the bit in the force reg.
}

void   norm_scr58_isr(void)	// norm_scr58_isr (58)
{
    if((NIPNDH & 0x04000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>8)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x04000000;		// clear the bit in the force reg.

}

void   norm_scr57_isr(void)	// norm_scr57_isr (57)
{
    if((NIPNDH & 0x02000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY7>>4)&0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x02000000;		// clear the bit in the force reg.

}

void   norm_scr56_isr(void)	// norm_scr56_isr (56)
{
    if((NIPNDH & 0x01000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if((NIPRIORITY7 & 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x01000000;		// clear the bit in the force reg.

}

void   norm_scr55_isr(void)	// norm_scr55_isr (55)
{
    if((NIPNDH & 0x00800000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>28)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00800000;		// clear the bit in the force reg.

}

void   norm_scr54_isr(void)	// norm_scr54_isr (54)
{
    if((NIPNDH & 0x00400000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>24)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00400000;		// clear the bit in the force reg.

}

void   norm_scr53_isr(void)	// norm_scr53_isr (53)
{
    if((NIPNDH & 0x00200000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>20)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00200000;		// clear the bit in the force reg.

}

void   norm_scr52_isr(void)	// norm_scr52_isr (52)
{
    if((NIPNDH & 0x00100000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>16)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00100000;		// clear the bit in the force reg.

}

void   norm_scr51_isr(void)	// norm_scr51_isr (51)
{
    if((NIPNDH & 0x00080000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>12)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00080000;		// clear the bit in the force reg.

}

void   norm_scr50_isr(void)	// norm_scr50_isr (50)
{
    if((NIPNDH & 0x00040000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>8)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00040000;		// clear the bit in the force reg.

}

void   norm_scr49_isr(void)	// norm_scr49_isr (49)
{
    if((NIPNDH & 0x00020000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6>>4)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00020000;		// clear the bit in the force reg.

}

void   norm_scr48_isr(void)	// norm_scr48_isr (48)
{
    if((NIPNDH & 0x00010000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY6)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00010000;		// clear the bit in the force reg.

}

void   norm_scr47_isr(void)	// norm_scr47_isr (47)
{
    if((NIPNDH & 0x00008000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>28)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00008000;		// clear the bit in the force reg.

}

void   norm_scr46_isr(void)	// norm_scr46_isr (46)
{
    if((NIPNDH & 0x00004000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>24)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00004000;		// clear the bit in the force reg.

}

void   norm_scr45_isr(void)	// norm_scr45_isr (45)
{
    if((NIPNDH & 0x00002000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>20)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00002000;		// clear the bit in the force reg.

}


void   norm_scr44_isr(void)	// norm_scr44_isr (44)
{
    if((NIPNDH & 0x00001000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>16)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00001000;

}


void   norm_scr43_isr(void)	// norm_scr43_isr (43)
{
    if((NIPNDH & 0x00000800) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>12)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00000800;		// clear the bit in the force reg.

}

void   norm_scr42_isr(void)	// norm_scr42_isr (42)
{
    if((NIPNDH & 0x00000400) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>8)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00000400;		// clear the bit in the force reg.

}

void   norm_scr41_isr(void)	// norm_scr41_isr (41)
{
    if((NIPNDH & 0x00000200) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5>>4)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00000200;		// clear the bit in the force reg.

}


void   norm_scr40_isr(void)	// norm_scr40_isr (40)
{
    if((NIPNDH & 0x00000100) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY5)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00000100;		// clear the bit in the force reg.

}

void   norm_scr39_isr(void)	// norm_scr39_isr (39)
{
    if((NIPNDH & 0x00000080) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((NIPRIORITY4>>28)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
	
    INTFRCH &= ~0x00000080;		// clear the bit in the force reg.

}

void   norm_scr38_isr(void)	// norm_scr38_isr (38)
{
    if((NIPNDH & 0x00000040) == 0)	// verify the pending bit is set
    {
        	gFailPendingCount++;
    }	
	
	if(((NIPRIORITY4>>24)& 0xF)!=(NIVECSR & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    INTFRCH &= ~0x00000040;		// clear the bit in the force reg.