chandle.c

How to detect Battery voltage in DragonBall SZ platform

/*
 * Copyright (C) ARM Limited, 1998. All rights reserved.
 */
#include <stdio.h>
#include "MX1_def.h"
#include "Common.h"
#include "ProtoType.h"


typedef void (*FUNCT)(void);		// define a pointer to a function

/* look up table of normal ISRs */
FUNCT vect_IRQ[64] = {norm_scr00_isr, norm_scr01_isr, norm_scr02_isr, norm_scr03_isr,  
					 norm_scr04_isr, norm_scr05_isr, norm_scr06_isr, norm_scr07_isr,
					 norm_scr08_isr, norm_scr09_isr, norm_scr10_isr, norm_scr11_isr,  
					 norm_scr12_isr, norm_scr13_isr, norm_scr14_isr, norm_scr15_isr,
					 norm_scr16_isr, norm_scr17_isr, norm_scr18_isr, norm_scr19_isr,  
					 norm_scr20_isr, norm_scr21_isr, norm_scr22_isr, norm_scr23_isr,
					 norm_scr24_isr, norm_scr25_isr, norm_scr26_isr, norm_scr27_isr,  
					 norm_scr28_isr, norm_scr29_isr, norm_scr30_isr, norm_scr31_isr,
					 norm_scr32_isr, norm_scr33_isr, norm_scr34_isr, norm_scr35_isr,  
					 norm_scr36_isr, norm_scr37_isr, norm_scr38_isr, norm_scr39_isr,
					 norm_scr40_isr, norm_scr41_isr, norm_scr42_isr, norm_scr43_isr,  
					 norm_scr44_isr, norm_scr45_isr, norm_scr46_isr, norm_scr47_isr,
					 norm_scr48_isr, norm_scr49_isr, norm_scr50_isr, norm_scr51_isr,  
					 norm_scr52_isr, norm_scr53_isr, norm_scr54_isr, norm_scr55_isr,
					 norm_scr56_isr, norm_scr57_isr, norm_scr58_isr, norm_scr59_isr, 
					 norm_scr60_isr, norm_scr61_isr, norm_scr62_isr, norm_scr63_isr};

/* look up table of fast ISRs */					 
FUNCT vect_FIQ[64] = {fast_scr00_isr, fast_scr01_isr, fast_scr02_isr, fast_scr03_isr,  
					 fast_scr04_isr, fast_scr05_isr, fast_scr06_isr, fast_scr07_isr,
					 fast_scr08_isr, fast_scr09_isr, fast_scr10_isr, fast_scr11_isr,  
					 fast_scr12_isr, fast_scr13_isr, fast_scr14_isr, fast_scr15_isr,
					 fast_scr16_isr, fast_scr17_isr, fast_scr18_isr, fast_scr19_isr,  
					 fast_scr20_isr, fast_scr21_isr, fast_scr22_isr, fast_scr23_isr,
					 fast_scr24_isr, fast_scr25_isr, fast_scr26_isr, fast_scr27_isr,  
					 fast_scr28_isr, fast_scr29_isr, fast_scr30_isr, fast_scr31_isr,
					 fast_scr32_isr, fast_scr33_isr, fast_scr34_isr, fast_scr35_isr,  
					 fast_scr36_isr, fast_scr37_isr, fast_scr38_isr, fast_scr39_isr,
					 fast_scr40_isr, fast_scr41_isr, fast_scr42_isr, fast_scr43_isr,  
					 fast_scr44_isr, fast_scr45_isr, fast_scr46_isr, fast_scr47_isr,
					 fast_scr48_isr, fast_scr49_isr, fast_scr50_isr, fast_scr51_isr,  
					 fast_scr52_isr, fast_scr53_isr, fast_scr54_isr, fast_scr55_isr,
					 fast_scr56_isr, fast_scr57_isr, fast_scr58_isr, fast_scr59_isr, 
					 fast_scr60_isr, fast_scr61_isr, fast_scr62_isr, fast_scr63_isr};
/******************************* Global Data *********************************/
#define NUM_INT_SOURCES	64
/* ISR flags */
volatile int gNormInt0flag;
volatile int gNormInt1flag;
volatile int gNormInt2flag;
volatile int gNormInt3flag;
volatile int gNormInt4flag;
volatile int gNormInt5flag;
volatile int gNormInt6flag;
volatile int gNormInt7flag;
volatile int gNormInt8flag;
volatile int gNormInt9flag;
volatile int gNormInt10flag;
volatile int gNormInt11flag;
volatile int gNormInt12flag;
volatile int gNormInt13flag;
volatile int gNormInt14flag;
volatile int gNormInt15flag;
volatile int gNormInt16flag;
volatile int gNormInt32flag;
volatile int gNormInt61flag;
volatile int gNormInt62flag;
volatile int gNormInt63flag;

volatile int gFastInt0flag;
volatile int gFastInt1flag;
volatile int gFastInt2flag;
volatile int gFastInt4flag;
volatile int gFastInt8flag;
volatile int gFastInt16flag;
volatile int gFastInt32flag;
volatile int gFastInt61flag;
volatile int gFastInt62flag;
volatile int gFastInt63flag;			

volatile int gFailFastCount;
volatile int gFailPendingCount;
volatile int gFailPriorityCount;
					 				
void C_SWI_Handler( int swi_num, int *regs )
{
    switch( swi_num )
    {
    	case 0:
    	break;
		default:
    	break;
    }
}


void C_Undefined_Handler(void)
{
	//read in ITC status reg
	//test bit for dispatch
	//call user ISR
	return;
}

void C_Prefetch_Handler(void)
{
	//read in ITC status reg
	//test bit for dispatch
	//call user ISR
	return;
}

void C_Abort_Handler(void)
{
	//read in ITC status reg
	//test bit for dispatch
	//call user ISR
	return;
}


/******************************************************************************
* IRQ_Handler                                                                 *
* This function handles IRQ interrupts.  				                      *
******************************************************************************/

void __irq C_IRQ_Handler(void)
{
	short vectNum;
	vectNum = NIVECSR >> 16;	// determine highest pending normal interrupt		
	vect_IRQ[vectNum]();		// find the pointer to correct ISR in the look up table
}

/******************************************************************************
* FIQ_Handler                                                                 *
* This function handles IRQ interrupts.  				                      *
******************************************************************************/

void __irq C_FIQ_Handler(void)
{
	short vectNum;
	vectNum = FIVECSR & 0x0000003F;	// determine highest pending fast interrupt
	vect_FIQ[vectNum]();		// find the pointer to correct ISR in the look up table
}


/*******************************************************************************
*
*  Interrupt Handlers (64 fast int sources and 64 normal int sources)
*
*******************************************************************************/


/***********************/
/* Fast Interrupt ISRs */
/***********************/


void   fast_scr31_isr(void)		// fast_scr31_isr (31)
{
    if((FIPNDL & 0x80000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x80000000;		// clear the bit in the force reg.
}

void   fast_scr63_isr(void)	// fast_scr63_isr (63)
{
    if((FIPNDH & 0x80000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x80000000;		// clear the bit in the force reg.
    gFastInt63flag = 1;				// set flag
}

void   fast_scr30_isr(void)	// fast_scr30_isr (30)
{
    if((FIPNDL & 0x40000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x40000000;		// clear the bit in the force reg.
}

void   fast_scr62_isr(void)	// fast_scr62_isr (62)
{
    if((FIPNDH & 0x40000000)== 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x40000000;		// clear the bit in the force reg.
    gFastInt62flag = 1;
}

void   fast_scr29_isr(void)	// fast_scr29_isr (29)
{
    if((FIPNDL & 0x20000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x20000000;		// clear the bit in the force reg.
}

void   fast_scr61_isr(void)	// fast_scr61_isr (61)
{
    if((FIPNDH & 0x20000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x20000000;		// clear the bit in the force reg.
}

void   fast_scr28_isr(void)	// fast_scr28_isr (28)
{
    if((FIPNDL & 0x10000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x10000000;		// clear the bit in the force reg.
}

void   fast_scr60_isr(void)	// fast_scr60_isr (60)
{
    if((FIPNDH & 0x10000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x10000000;		// clear the bit in the force reg.
}

void   fast_scr27_isr(void)	// fast_scr27_isr (27)
{
    if((FIPNDL & 0x08000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x08000000;		// clear the bit in the force reg.
}

void   fast_scr59_isr(void)	// fast_scr59_isr (59)
{
    if((FIPNDH & 0x08000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x08000000;		// clear the bit in the force reg.
}

void   fast_scr26_isr(void)	// fast_scr26_isr (26)
{
    if((FIPNDL & 0x04000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x04000000;		// clear the bit in the force reg.
}

void   fast_scr58_isr(void)	// fast_scr58_isr (58)
{
    if((FIPNDH & 0x04000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x04000000;		// clear the bit in the force reg.
}

void   fast_scr25_isr(void)	// fast_scr25_isr (25)
{
    if((FIPNDL & 0x02000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x02000000;		// clear the bit in the force reg.
}

void   fast_scr57_isr(void)	// fast_scr57_isr (57)
{
    if((FIPNDH & 0x02000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x02000000;		// clear the bit in the force reg.
}

void   fast_scr24_isr(void)	// fast_scr24_isr (24)
{
    if((FIPNDL & 0x01000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x01000000;		// clear the bit in the force reg.
}

void   fast_scr56_isr(void)	// fast_scr56_isr (56)
{
    if((FIPNDH & 0x01000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x01000000;		// clear the bit in the force reg.
}

void   fast_scr23_isr(void)	// fast_scr23_isr (23)
{
    if((FIPNDL & 0x00800000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00800000;		// clear the bit in the force reg.
}

void   fast_scr55_isr(void)	// fast_scr55_isr (55)
{
    if((FIPNDH & 0x00800000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00800000;		// clear the bit in the force reg.
}

void   fast_scr22_isr(void)	// fast_scr22_isr (22)
{
    if((FIPNDL & 0x00400000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00400000;		// clear the bit in the force reg.
}

void   fast_scr54_isr(void)	// fast_scr54_isr (54)
{
    if((FIPNDH & 0x00400000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00400000;		// clear the bit in the force reg.
}

void   fast_scr21_isr(void)	// fast_scr21_isr (21)
{
    if((FIPNDL & 0x00200000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00200000;		// clear the bit in the force reg.
}

void   fast_scr53_isr(void)	// fast_scr53_isr (53)
{
    if((FIPNDH & 0x00200000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00200000;		// clear the bit in the force reg.
}

void   fast_scr20_isr(void)	// fast_scr20_isr (20)
{
    if((FIPNDL & 0x00100000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00100000;		// clear the bit in the force reg.
}

void   fast_scr52_isr(void)	// fast_scr52_isr (52)
{
    if((FIPNDH & 0x00100000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00100000;		// clear the bit in the force reg.
}

void   fast_scr19_isr(void)	// fast_scr19_isr (19)
{
    if((FIPNDL & 0x00080000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00080000;		// clear the bit in the force reg.
}

void   fast_scr51_isr(void)	// fast_scr51_isr (51)
{
    if((FIPNDH & 0x00080000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00080000;		// clear the bit in the force reg.
}

void   fast_scr18_isr(void)	// fast_scr18_isr (18)
{
    if((FIPNDL & 0x00040000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00040000;		// clear the bit in the force reg.
}

void   fast_scr50_isr(void)	// fast_scr50_isr (50)
{
    if((FIPNDH & 0x00040000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00040000;		// clear the bit in the force reg.
}

void   fast_scr17_isr(void)	// fast_scr17_isr (17)
{
    if((FIPNDL & 0x00020000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00020000;		// clear the bit in the force reg.
}

void   fast_scr49_isr(void)	// fast_scr49_isr (49)
{
    if((FIPNDH & 0x00020000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00020000;		// clear the bit in the force reg.
}

void   fast_scr16_isr(void)	// fast_scr16_isr (16)
{
    if((FIPNDL & 0x00010000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00010000;		// clear the bit in the force reg.
    gFastInt16flag = 1;
}

void   fast_scr48_isr(void)	// fast_scr48_isr (48)
{
    if((FIPNDH & 0x00010000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00010000;		// clear the bit in the force reg.
}

void   fast_scr15_isr(void)	// fast_scr15_isr (15)
{
    if((FIPNDL & 0x00008000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00008000;		// clear the bit in the force reg.
}

void   fast_scr47_isr(void)	// fast_scr47_isr (47)
{
    if((FIPNDH & 0x00008000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00008000;		// clear the bit in the force reg.
}

void   fast_scr14_isr(void)	// fast_scr14_isr (14)
{
    if((FIPNDL & 0x00004000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00004000;		// clear the bit in the force reg.
}

void   fast_scr46_isr(void)	// fast_scr46_isr (46)
{
    if((FIPNDH & 0x00004000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00004000;		// clear the bit in the force reg.
}

void   fast_scr13_isr(void)	// fast_scr13_isr (13)
{
    if((FIPNDL & 0x00002000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00002000;		// clear the bit in the force reg.
}

void   fast_scr45_isr(void)	// fast_scr45_isr (45)
{
    if((FIPNDH & 0x00002000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00002000;		// clear the bit in the force reg.
}

void   fast_scr12_isr(void)	// fast_scr12_isr (12)
{
    if((FIPNDL & 0x00001000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00001000;		// clear the bit in the force reg.
}

void   fast_scr44_isr(void)	// fast_scr44_isr (44)
{
    if((FIPNDH & 0x00001000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00001000;		// clear the bit in the force reg.
}

void   fast_scr11_isr(void)	// fast_scr11_isr (11)
{
    if((FIPNDL & 0x00000800) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000800;		// clear the bit in the force reg.
}

void   fast_scr43_isr(void)	// fast_scr43_isr (43)
{
    if((FIPNDH & 0x00000800) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000800;		// clear the bit in the force reg.
}

void   fast_scr10_isr(void)	// fast_scr10_isr (10)
{
    if((FIPNDL & 0x00000400) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000400;		// clear the bit in the force reg.
}

void   fast_scr42_isr(void)	// fast_scr42_isr (42)
{
    if((FIPNDH & 0x00000400) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCH &= ~0x00000400;		// clear the bit in the force reg.
}

void   fast_scr09_isr(void)	// fast_scr09_isr  (9)
{
    if((FIPNDL & 0x00000200) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

    INTFRCL &= ~0x00000200;		// clear the bit in the force reg.
}

void   fast_scr41_isr(void)	// fast_scr41_isr (41)
{
    if((FIPNDH & 0x00000200) == 0)	// verify the pending bit is set
    {