📄 reset_szads_128ni.s
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move.b #$00,PMSEL ; All are dedicated IO
move.b #$01,PNSEL ; PN0 as GPIO output for LED3
move.b #$01,PNDIR ; Direction of PN0 is output
move.b #$FE,PNPUEN ; Disable PN0's pull-up
move.b #$00,PNDATA ; PN0 as "0"
move.b #$00,PPSEL ; All are dedicated IO
move.b #$00,PRSEL ; All are dedicated IO
;*****************************
; Init Code for 4Mx16 Flash
;*****************************
move.w #$0400,GRPBASEA ; GROUPA BASE A(FLASH), Start address=64M
move.w #$01BB,CSA ; 8MB each, 6ws, FLASH,
;*****************************
; Init Code for 100K ESRAM
;*****************************
move.w #$0500,GRPBASEG ; GROUPA BASE(ESRAM), Start address=80M
move.w #$0001,CSG
;**********************************
; Init Code for EMUCS
;**********************************
move.w #$0060,EMUCS ; 12ws
move.w #$1000,CSCTRL1 ; No SRAM config
;####################################################
; #
; Init SDRAM0, 8Mx16,IAM=0,ROW=12,COL=9 #
; Cas Latency=2,Chip Select CSE #
; #
;####################################################
;Set current driver of SDRAM signals to 8mA
move.w #$0340,IODCR ;PG/PK/PM set to 8mA
;#### CSE For SDRAM0 #####
move.w #$0000,GRPBASEE ;Group Base Addr 0M
; move.w #$029B,CSE ;for 12row x 8col
move.w #$029d,CSE ;for 12row x 9col
; move.w #$029f,CSE ;for 13row x 9col
;#### DRAMC Init #####
move.w #$0000,SECTL ;non-interleave
; move.w #$0100,SECTL ;interleave
; move.w #$9100,SDCTLE_H ;for 12row x 8col, non-interleave
move.w #$9110,SDCTLE_H ;for 12row x 9col, non-interleave
; move.w #$9210,SDCTLE_H ;for 13row x 9col, non-interleave
; move.w #$9108,SDCTLE_H ;for 12row x 8col, interleave
; move.w #$9118,SDCTLE_H ;for 12row x 9col, interleave
; move.w #$9218,SDCTLE_H ;for 13row x 9col, interleave
move.w #$4200,SDCTLE_L ;non-interleave
; move.w #$4262,SDCTLE_L ;interleave
;#### issue precharge all and assert A10 ####
; move.b #$00,$00080000 ;for 12row x 8col, non-interleave
move.b #$00,$00100000 ;for 12row x 9col, non-interleave
; move.b #$00,$00100000 ;for 13row x 9col, non-interleave
; move.b #$00,$00200000 ;for 12row x 8col, interleave
; move.b #$00,$00400000 ;for 12row x 9col, interleave
; move.b #$00,$00400000 ;for 13row x 9col, interleave
;#### set auto refresh #####
; move.w #$A100,SDCTLE_H ;for 12row x 8col, non-interleave
move.w #$A110,SDCTLE_H ;for 12row x 9col, non-interleave
; move.w #$A210,SDCTLE_H ;for 13row x 9col, non-interleave
; move.w #$A108,SDCTLE_H ;for 12row x 8col, interleave
; move.w #$A118,SDCTLE_H ;for 12row x 9col, interleave
; move.w #$A218,SDCTLE_H ;for 13row x 9col, interleave
move.b #$00,$00000000 ;refresh
move.b #$00,$00000000 ;refresh
move.b #$00,$00000000 ;refresh
move.b #$00,$00000000 ;refresh
;###### set mode register #####
; move.w #$B100,SDCTLE_H ;for 12row x 8col, non-interleave
move.w #$B110,SDCTLE_H ;for 12row x 9col, non-interleave
; move.w #$B210,SDCTLE_H ;for 13row x 9col, non-interleave
; move.w #$B108,SDCTLE_H ;for 12row x 8col, interleave
; move.w #$B118,SDCTLE_H ;for 12row x 9col, interleave
; move.w #$B218,SDCTLE_H ;for 13row x 9col, interleave
; move.b #$00,$00044400 ;for 12row x 8col, non-interleave
move.b #$00,$00088800 ;for 12row x 9col, non-interleave
; move.b #$00,$00088800 ;for 13row x 9col, non-interleave
; move.b #$00,$00111000 ;for 12row x 8col, interleave
; move.b #$00,$00222000 ;for 12row x 9col, interleave
; move.b #$00,$00222000 ;for 13row x 9col, interleave
;##### return to normal mode #####
; move.w #$8100,SDCTLE_H ;for 12row x 8col, non-interleave
move.w #$8110,SDCTLE_H ;for 12row x 9col, non-interleave
; move.w #$8210,SDCTLE_H ;for 13row x 9col, non-interleave
; move.w #$8108,SDCTLE_H ;for 12row x 8col, interleave
; move.w #$8118,SDCTLE_H ;for 12row x 9col, interleave
; move.w #$8218,SDCTLE_H ;for 13row x 9col, interleave
;# DELAY some time after SDRAM0 init
movea.l #$00010000,a0 ;set delay time
bsr DELAY
;######################################################
; #
; Init SDRAM1, 8Mx16,IAM=0,ROW=12,COL=9 #
; Cas Latency=2,Chip Select CSF #
; #
;######################################################
;Current driver of SDRAM signals has been set to 8mA
;# Has been set by SDRAM0 init
;# move.w #$0340,$FFFFF008 ;PG/PK/PM set to 8mA
;#### CSF For SDRAM1 #####
; move.w #$0080,GRPBASEF ;Group Base Addr 8M for 12row x 8col
move.w #$0100,GRPBASEF ;Group Base Addr 16M for 12row x 9col
; move.w #$0200,GRPBASEF ;Group Base Addr 32M for 13row x 9col
; move.w #$029B,CSF ;for 12row x 8col
move.w #$029d,CSF ;for 12row x 9col
; move.w #$029f,CSF ;for 13row x 9col
;#### DRAMC Init #####
;# Has been set by SDRAM0 init
;# move.w #$0000,SECTL ;non-interleave
;# move.w #$0100,SECTL ;interleave
; move.w #$9100,SDCTLF_H ;for 12row x 8col, non-interleave
move.w #$9110,SDCTLF_H ;for 12row x 9col, non-interleave
; move.w #$9210,SDCTLF_H ;for 13row x 9col, non-interleave
; move.w #$9108,SDCTLF_H ;for 12row x 8col, interleave
; move.w #$9118,SDCTLF_H ;for 12row x 9col, interleave
; move.w #$9218,SDCTLF_H ;for 13row x 9col, interleave
move.w #$4200,SDCTLF_L ;non-interleave
; move.w #$4262,SDCTLF_L ;interleave
;#### issue precharge all and assert A10 ####
; move.b #$00,$00080000 ;for 12row x 8col, non-interleave
move.b #$00,$01100000 ;for 12row x 9col, non-interleave
; move.b #$00,$02100000 ;for 13row x 9col, non-interleave
; move.b #$00,$00200000 ;for 12row x 8col, interleave
; move.b #$00,$01400000 ;for 12row x 9col, interleave
; move.b #$00,$02400000 ;for 13row x 9col, interleave
;#### set auto refresh #####
; move.w #$A100,SDCTLF_H ;for 12row x 8col, non-interleave
move.w #$A110,SDCTLF_H ;for 12row x 9col, non-interleave
; move.w #$A210,SDCTLF_H ;for 13row x 9col, non-interleave
; move.w #$A108,SDCTLF_H ;for 12row x 8col, interleave
; move.w #$A118,SDCTLF_H ;for 12row x 9col, interleave
; move.w #$A218,SDCTLF_H ;for 13row x 9col, interleave
; move.b #$00,$00800000 ;refresh for 12row x 8col
; move.b #$00,$00800000 ;refresh for 12row x 8col
; move.b #$00,$00800000 ;refresh for 12row x 8col
; move.b #$00,$00800000 ;refresh for 12row x 8col
move.b #$00,$01000000 ;refresh for 12row x 9col
move.b #$00,$01000000 ;refresh for 12row x 9col
move.b #$00,$01000000 ;refresh for 12row x 9col
move.b #$00,$01000000 ;refresh for 12row x 9col
; move.b #$00,$02000000 ;refresh for 13row x 9col
; move.b #$00,$02000000 ;refresh for 13row x 9col
; move.b #$00,$02000000 ;refresh for 13row x 9col
; move.b #$00,$02000000 ;refresh for 13row x 9col
;###### set mode register #####
; move.w #$B100,SDCTLF_H ;for 12row x 8col, non-interleave
move.w #$B110,SDCTLF_H ;for 12row x 9col, non-interleave
; move.w #$B210,SDCTLF_H ;for 13row x 9col, non-interleave
; move.w #$B108,SDCTLF_H ;for 12row x 8col, interleave
; move.w #$B118,SDCTLF_H ;for 12row x 9col, interleave
; move.w #$B218,SDCTLF_H ;for 13row x 9col, interleave
; move.b #$00,$00844400 ;for 12row x 8col, non-interleave
move.b #$00,$01088800 ;for 12row x 9col, non-interleave
; move.b #$00,$02088800 ;for 13row x 9col, non-interleave
; move.b #$00,$00911000 ;for 12row x 8col, interleave
; move.b #$00,$01222000 ;for 12row x 9col, interleave
; move.b #$00,$02222000 ;for 13row x 9col, interleave
;##### return to normal mode #####
; move.w #$8100,SDCTLF_H ;for 12row x 8col, non-interleave
move.w #$8110,SDCTLF_H ;for 12row x 9col, non-interleave
; move.w #$8210,SDCTLF_H ;for 13row x 9col, non-interleave
; move.w #$8108,SDCTLF_H ;for 12row x 8col, interleave
; move.w #$8118,SDCTLF_H ;for 12row x 9col, interleave
; move.w #$8218,SDCTLF_H ;for 13row x 9col, interleave
;# DELAY some time after SDRAM1 init
movea.l #$00010000,a0 ;set delay time
bsr DELAY
;**********************************************************
; Copy SSP and PC from Flash to SDRAM
; Only for SZ328 Ver1.0/1.1/1.2
;**********************************************************
movea.l #$04000000,a0 ;set source address
movea.l #$00000000,a1 ;set destination address
move.w (a0)+,D0
move.w D0,(a1)+
move.w (a0)+,D0
move.w D0,(a1)+
move.w (a0)+,D0
move.w D0,(a1)+
move.w (a0)+,D0
move.w D0,(a1)+
nop
;**********************************************************************
; 4 bit LCD_Init for Display BMP Image
;**********************************************************************
; move.l #$05000000,SZ_LSSA
; move.w #$28F0,SZ_LSS ;XMAX=20 x 8; YAMX=240;
; move.w #$000A,SZ_LVPW ;VPW=10 x 16;
; move.w #$0002,SZ_LPCON0
; move.w #$2100,SZ_LPCON1
; move.w #$0000,SZ_LHCON0 ; ???
; move.w #$0400,SZ_LHCON1 ; ???
; move.w #$0000,SZ_LVCON0 ; ???
; move.w #$0401,SZ_LVCON1 ; ???
; move.w #$0000,SZ_RMCR ; disable LCDC
; move.w #$0002,SZ_RMCR ; enable LCDC, 0ws, 16-bit
;**********************************************************************
; 16 bit LCD_Init for Display BMP Image
;**********************************************************************
move.l #$01000000,SZ_LSSA
move.w #$50F0,SZ_LSS ;XMAX=320/8=40, YMAX=240=0xF0
move.w #$0140,SZ_LVPW ;VPW=320*16/16;
move.w #$8B09,SZ_LPCON0
move.w #$F805,SZ_LPCON1
move.w #$0200,SZ_PWMR
move.w #$0F06,SZ_LHCON0 ; ???
move.w #$0400,SZ_LHCON1 ; ???
move.w #$0B03,SZ_LVCON0 ; ???
move.w #$0401,SZ_LVCON1 ; ???
move.w #$0000,SZ_LCXP ; ???
move.w #$0000,SZ_LCSR ; ???
move.w #$000F,SZ_LCUR_COL ; ???
move.w #$0002,SZ_RMCR ; enable LCDC, 0ws, 16-bit
; movea.l #$0401003E,a0 ;set source address of 4 bit LCD
; movea.l #$05000000,a1 ;set destination address
; movea.l #IMAGE4_SIZE,a2 ;set size
movea.l #$04010000,a0 ;set source address of 16 bit LCD
movea.l #$01000000,a1 ;set destination address
movea.l #IMAGE16_SIZE,a2 ;set size
bsr IMAGE_COPY
movea.l #$00050000,a0 ;set delay time
bsr DELAY
move.b #$01,PKDATA ; PK0 as "1" to pull high TFTEN
bra FINISH
;**********************************************************************
DELAY:
move.l d0,-(a7) ; Push d0
clr.l d0
DELAY_LP:
addi.l #1,d0
cmp.l a0,d0
bne DELAY_LP
move.l (a7)+,d0 ; Restore d0
rts
;**********************************************************************
IMAGE_COPY:
move.l d0,-(a7) ; Push d0
move.l d1,-(a7) ; Push d1
move.l a3,-(a7) ; Push a3
move.l a4,-(a7) ; Push a4
clr.l d0
IMAGE_COPY_LP:
move.w (a0)+,d1
move.w d1,(a1)+
addi.l #1,d0
cmp.l d0,a2
bne IMAGE_COPY_LP
move.l (a7)+,a4 ; Restore a4
move.l (a7)+,a3 ; Restore a3
move.l (a7)+,d1 ; Restore d1
move.l (a7)+,d0 ; Restore d0
rts
;**********************************************************************
; Clear all data register
;**********************************************************************
FINISH:
clr.l d0
clr.l d1
clr.l d2
clr.l d3
clr.l d4
clr.l d5
clr.l d6
clr.l d7
.extern __start
JMP __start ; jump to MW startup code
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