📄 reset_szads_128ni.s
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;***************************************************************
; File Name: Reset_SZADS_128NI.S
; Descriptions: MetroWerks initcode for M68SZ328ADS Ver1.0
; Version: 0.3
; Date: 10/25/2001
; Updated by: Shark Wu
;***************************************************************
MON_STACKTOP .equ $4100 ; Above is TOO low, try this
M328BASE .equ $FFFFF000
; SIM28 System Configuration Registers
SCR .equ (M328BASE+$000)
; Chip Select Registers
GRPBASEA .equ (M328BASE+$100)
GRPBASEB .equ (M328BASE+$102)
GRPBASEC .equ (M328BASE+$104)
GRPBASED .equ (M328BASE+$106)
CSA .equ (M328BASE+$110)
CSB .equ (M328BASE+$112)
CSC .equ (M328BASE+$114)
CSD .equ (M328BASE+$116)
DRAMCFG .equ (M328BASE+$C00)
DRAMCTL .equ (M328BASE+$C02)
EMUCS .equ (M328BASE+$118)
CSCTR .equ (M328BASE+$150)
; PLL Registers
PLLCR .equ (M328BASE+$200) ; Control Reg
PLLFSR .equ (M328BASE+$202) ; Freq Select Reg
PLLTSR .equ (M328BASE+$204) ; Test Reg
; Power Control Registers
PCTLR .equ (M328BASE+$206) ; Control Reg
; Interrupt Registers
IVR .equ (M328BASE+$300) ; Interrupt Vector Reg
ICR .equ (M328BASE+$302) ; Interrupt Control Reg
IMR .equ (M328BASE+$304) ; Interrupt Mask Reg
ISR .equ (M328BASE+$30C) ; Interrupt Status Reg
IPR .equ (M328BASE+$310) ; Interrupt Pending Reg
; PIO Registers
; Port A Registers
PADIR .equ (M328BASE+$400) ; Direction Reg
PADATA .equ (M328BASE+$401) ; Data Reg
PAPUEN .equ (M328BASE+$402) ; Pullup Enable Reg
; Port B Registers
PBDIR .equ (M328BASE+$408) ; Direction Reg
PBDATA .equ (M328BASE+$409) ; Data Reg
PBPUEN .equ (M328BASE+$40A) ; Pullup Enable Reg
PBSEL .equ (M328BASE+$40B) ; Select Reg
; Port C Registers
PCDIR .equ (M328BASE+$410) ; Direction Reg
PCDATA .equ (M328BASE+$411) ; Data Reg
PCPDEN .equ (M328BASE+$412) ; Pull-down Enable Reg
PCSEL .equ (M328BASE+$413) ; Select Reg
; Port D Registers
PDDIR .equ (M328BASE+$418) ; Direction Reg
PDDATA .equ (M328BASE+$419) ; Data Reg
PDPUEN .equ (M328BASE+$41A) ; Pullup Enable Reg
PDSEL .equ (M328BASE+$41B) ; port D select
PDPOL .equ (M328BASE+$41C) ; Polarity Reg
PDIRQEN .equ (M328BASE+$41D) ; IRQ Enable Reg
PDIRQEDGE .equ (M328BASE+$41F) ; IRQ Edge Reg
; Port E Registers
PEDIR .equ (M328BASE+$420) ; Direction Reg
PEDATA .equ (M328BASE+$421) ; Data Reg
PEPUEN .equ (M328BASE+$422) ; Pullup Enable Reg
PESEL .equ (M328BASE+$423) ; Select Reg
; Port F Registers
PFDIR .equ (M328BASE+$428) ; Direction Reg
PFDATA .equ (M328BASE+$429) ; Data Reg
PFPUEN .equ (M328BASE+$42A) ; Pullup Enable Reg
PFSEL .equ (M328BASE+$42B) ; Select Reg
; Port G Registers
PGDIR .equ (M328BASE+$430) ; Direction Reg
PGDATA .equ (M328BASE+$431) ; Data Reg
PGPUEN .equ (M328BASE+$432) ; Pullup Enable Reg
PGSEL .equ (M328BASE+$433) ; Select Reg
; PWM Registers
PWMC .equ (M328BASE+$500) ; Control Reg
PWMS .equ (M328BASE+$502) ; Sample Reg
PWMCNT .equ (M328BASE+$504) ; Count Reg
; Timer Registers
; Timer 1 Registers
TCTL .equ (M328BASE+$600) ; Control Reg
TPRER .equ (M328BASE+$602) ; Prescalar Reg
TCMP .equ (M328BASE+$604) ; Compare Reg
TCR .equ (M328BASE+$606) ; Capture Reg
TCN .equ (M328BASE+$608) ; Counter
TSTAT .equ (M328BASE+$60A) ; Status Reg
; SPI Registers
SPIMDATA .equ (M328BASE+$800) ; Control/Status Reg
SPIMCONT .equ (M328BASE+$802) ; Data Reg
; UART Registers
USTCNT .equ (M328BASE+$900) ; Status Control Reg
UBAUD .equ (M328BASE+$902) ; Baud Control Reg
UARTRX .equ (M328BASE+$904) ; Rx Reg
UARTTX .equ (M328BASE+$906) ; Tx Reg
UARTMISC .equ (M328BASE+$908) ; Misc Reg
UARTNIPR .equ (M328BASE+$90A) ; None-Integer Prscaler reg
; LCDC Registers
LSSA .equ (M328BASE+$A00) ; Screen Start Addr Reg
LVPW .equ (M328BASE+$A05) ; Virtual Page Width Reg
LXMAX .equ (M328BASE+$A08) ; Screen Width Reg
LYMAX .equ (M328BASE+$A0A) ; Screen Height Reg
LCXP .equ (M328BASE+$A18) ; Cursor X Position
LCYP .equ (M328BASE+$A1A) ; Cursor Y Position
LCWCH .equ (M328BASE+$A1C) ; Cursor Width & Height Reg
LBLKC .equ (M328BASE+$A1F) ; Blink Control Reg
LPICF .equ (M328BASE+$A20) ; Panel Interface Config Reg
LPOLCF .equ (M328BASE+$A21) ; Polarity Config Reg
LACDRC .equ (M328BASE+$A23) ; ACD (M) Rate Control Reg
LPXCD .equ (M328BASE+$A25) ; Pixel Clock Divider Reg
LCKCON .equ (M328BASE+$A27) ; Clocking Control Reg
LRRA .equ (M328BASE+$A29) ; Refresh Rate Adjust reg
LPOSR .equ (M328BASE+$A2D) ; Panning Offset Reg
LFRCM .equ (M328BASE+$A31) ; Frame Rate Control Mod Reg
LGPMR .equ (M328BASE+$A33) ; Gray Palette Mapping Reg
LPWM .equ (M328BASE+$A36) ; contrast control Reg
; RTC Registers
RTCHMSR .equ (M328BASE+$B00) ; Hrs Mins Secs Reg
RTCALM0R .equ (M328BASE+$B04) ; Alarm Register
RTCDAY .equ (M328BASE+$B08) ; RTC date reg
RTCWD .equ (M328BASE+$B0A) ; RTC watch dog timer reg
RTCCTL .equ (M328BASE+$B0C) ; Control Reg
RTCISR .equ (M328BASE+$B0E) ; Interrupt Status Reg
RTCIENR .equ (M328BASE+$B10) ; Interrupt Enable Reg
RSTPWCH .equ (M328BASE+$B12) ; Stopwatch Minutes
;ICEM registers
ICEMACR .equ (M328BASE+$D00)
ICEMAMR .equ (M328BASE+$D04)
ICEMCCR .equ (M328BASE+$D08)
ICEMCMR .equ (M328BASE+$D0A)
ICEMCR .equ (M328BASE+$D0C)
ICEMSR .equ (M328BASE+$D0E)
******************************************************************************
* Register Special for SZ328
******************************************************************************
SZ328BASE .equ $FFFE0000
CSCR .equ (M328BASE+$20C) ; CSCR Reg
IODCR .equ (M328BASE+$008) ; IODCR Reg
GRPBASEE .equ (M328BASE+$180)
CSE .equ (M328BASE+$190)
GRPBASEF .equ (M328BASE+$182)
CSF .equ (M328BASE+$192)
GRPBASEG .equ (M328BASE+$184)
CSG .equ (M328BASE+$194)
CSCTRL1 .equ (M328BASE+$18A)
CSCTRL .equ (M328BASE+$10A)
SECTL .equ (M328BASE+$C10)
SDCTLE_L .equ (M328BASE+$C02)
SDCTLE_H .equ (M328BASE+$C00)
SDCTLF_L .equ (M328BASE+$C06)
SDCTLF_H .equ (M328BASE+$C04)
SZ_LSSA .equ (SZ328BASE+$800)
SZ_LSS .equ (SZ328BASE+$804)
SZ_LVPW .equ (SZ328BASE+$806)
SZ_LCXP .equ (SZ328BASE+$808)
SZ_LCYP .equ (SZ328BASE+$80A)
SZ_LCSR .equ (SZ328BASE+$80C)
SZ_LBLKC .equ (SZ328BASE+$80E)
SZ_LCUR_COL .equ (SZ328BASE+$810)
SZ_LPCON0 .equ (SZ328BASE+$812)
SZ_LPCON1 .equ (SZ328BASE+$814)
SZ_LHCON0 .equ (SZ328BASE+$816)
SZ_LHCON1 .equ (SZ328BASE+$818)
SZ_LVCON0 .equ (SZ328BASE+$81A)
SZ_LVCON1 .equ (SZ328BASE+$81C)
SZ_LPANOFF .equ (SZ328BASE+$81E)
SZ_LPGPMR .equ (SZ328BASE+$820)
SZ_PWMR .equ (SZ328BASE+$822)
SZ_LDMACR .equ (SZ328BASE+$824)
SZ_RMCR .equ (SZ328BASE+$826)
SZ_LICFR .equ (SZ328BASE+$828)
SZ_LISR .equ (SZ328BASE+$82A)
PJDIR .equ (M328BASE+$438) ; Direction Reg
PJDATA .equ (M328BASE+$439) ; Data Reg
PJPUEN .equ (M328BASE+$43A) ; Pullup Enable Reg
PJSEL .equ (M328BASE+$43B) ; Select Reg
PKDIR .equ (M328BASE+$440) ; Direction Reg
PKDATA .equ (M328BASE+$441) ; Data Reg
PKPUEN .equ (M328BASE+$442) ; Pullup Enable Reg
PKSEL .equ (M328BASE+$443) ; Select Reg
PMDIR .equ (M328BASE+$448) ; Direction Reg
PMDATA .equ (M328BASE+$449) ; Data Reg
PMPUEN .equ (M328BASE+$44A) ; Pullup Enable Reg
PMSEL .equ (M328BASE+$44B) ; Select Reg
PNDIR .equ (M328BASE+$450) ; Direction Reg
PNDATA .equ (M328BASE+$451) ; Data Reg
PNPUEN .equ (M328BASE+$452) ; Pullup Enable Reg
PNSEL .equ (M328BASE+$453) ; Select Reg
PPDIR .equ (M328BASE+$458) ; Direction Reg
PPDATA .equ (M328BASE+$459) ; Data Reg
PPPUEN .equ (M328BASE+$45A) ; Pullup Enable Reg
PPSEL .equ (M328BASE+$45B) ; Select Reg
PRDIR .equ (M328BASE+$460) ; Direction Reg
PRDATA .equ (M328BASE+$461) ; Data Reg
PRPUEN .equ (M328BASE+$462) ; Pullup Enable Reg
PRSEL .equ (M328BASE+$463) ; Select Reg
******************************************************************************
* BMP image size
******************************************************************************
IMAGE4_SIZE .equ $12C0 ; 4 bit BMP image size is 320x240 words
IMAGE16_SIZE .equ $12C00 ; 16 bit BMP image size is 320x240 words
ESRAM_SIZE .equ $C400 ; ESRAM size is $18800 bytes
******************************************************************************
* RESET OPTIONS
******************************************************************************
.section .reset
rom_base:
;-- SECTION rom_reset - SP, start addr & space for Exception Vectors
.DC.L MON_STACKTOP ; stack pointer
.DC.L rom_start ; program counter
.skip (62*4) ; space for Motorola defined Exception Vectors
.skip (192*4) ; space for the 192 User defined Exception Vectors
;-- SECTION rom_code
.global ___reset
___reset:
rom_start:
move.l #MON_STACKTOP,A7 ; Install stack pointer
move.w #$2700,sr ; mask off all interrupts
move.b #$18,SCR ; enable bus error timeout bit, disable DMAP
move.w #0,RTCWD ; disable watch dog
;**********************************************************************
; Set DMACLK/SYSCLK/CPUCLK/LCDCLK/USBCLK
;**********************************************************************
; move.w #$8903,CSCR ; DMACLK = MCUPLLCLK/4 = 16MHZ
; move.w #$8803,CSCR ; DMACLK = MCUPLLCLK/2 = 33MHZ
move.w #$8C03,CSCR ; DMACLK = MCUPLLCLK/1 = 66MHZ
;**************************************
; Init Code for ICE Module
;**************************************
move.w #$08,ICEMCR ; disable ICEM vector hardmap
move.w #$07,ICEMSR ; clear level 7 interrupt
;**********************************************************************
; Program Interrupt Controller
;**********************************************************************
move.b #$40,IVR
move.l #$FF7FFFFF,IMR ;disable all interrupt except ~EMUIRQ
;**************************************
; Init Code for GPIO and Dedicated IO
;**************************************
move.b #$70,PBSEL ; PB4/PB5/PB6 as GPIO input for user defined purpose
move.b #$00,PBDIR ; Direction of PB4/PB5/PB6 are input
move.b #$FF,PBPUEN ; PB4/PB5/PB6 should be pulled up if user want to use them
move.b #$00,PCSEL ; All are dedicated IO
move.b #$F0,PDSEL ; PD4/PD5/PD6/PD7 as GPIO input for keypad
move.b #$00,PDDIR ; Direction of PD4/PD5/PD6/PD7 are input
move.b #$FF,PDPUEN ; PD4/PD5/PD6/PD7 should be pulled up
move.b #$0B,PESEL ; PE0/PE1/PE3 as GPIO output for UARTx/IrDA transceiver enable
move.b #$0B,PEDIR ; Direction of PE0/PE1/PE3 are output
move.b #$F4,PEPUEN ; Disable PE0/PE1/PE3's pull-up
move.b #$F4,PEDATA ; PE0/PE1/PE3 as "0" to enable UARTx/IrDA transceiver
move.b #$02,PFSEL ; PF1 as GPIO output for LED4
move.b #$02,PFDIR ; Direction of PF1 is output
move.b #$FD,PFPUEN ; Disable PF1's pull-up
move.b #$00,PFDATA ; PF1 as "0"
move.b #$2B,PGSEL ; PG0/PG1 as GPIO input for keypad, PG3/PG5 as GPIO input for SD/MMC detect
move.b #$00,PGDIR ; Direction of PG0/PG1/PG3/PG5 are input
move.b #$FF,PGPUEN ; PG0/PG1/PG3/PG5 should be pulled up
move.b #$0F,PJSEL ; PJ0/PJ1/PJ2/PJ3 as GPIO input for keypad
move.b #$00,PJDIR ; Direction of PJ0/PJ1/PJ2/PJ3 are input
move.b #$FF,PJPUEN ; PJ0/PJ1/PJ2/PJ3 should be pulled up
move.b #$01,PKSEL ; PK0 as GPIO output for TFTEN
move.b #$01,PKDIR ; Direction of PK0 is output
move.b #$FE,PKPUEN ; Disable PK0's pull-up
move.b #$00,PKDATA ; PK0 as "0" to pull low TFTEN
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