tms470r1b1m_can_03.c

TMS-FET470B1M C Examples

//------------------------------------------------------------------------------
// tms470r1b1m_CAN_03.c - CAN Monitor Demo
//
// Description: This demo code serves as a simple CAN bus monitor. It uses the
// High End CAN controller 1 (HECC1) to receive any incoming CAN messages (with
// both 11-bit and 29-bit identifiers) using interrupts. These messages are
// decoded and output as text to the SCI1 module for display in a terminal
// program such as HyperTerm.
//
//  SYSCLK = MCLK = ACLK = 8 x 7.3728MHz = 58.9824MHz
//  ICLK = SYSCLK / 2 = 29.4912MHz
//
//  //*An external 7.3728MHz XTAL with proper load caps is required*//	
//
//            TMS-FET470B1M
//          +---------------+
//          |          OSCIN|-
//       +--|PLLDIS         | 7.3728MHz
//       |  |         OSCOUT|-
//      -+- |               |
//          |         SCI1TX|------------>
//          |               | 115200 - 8N1
//          |         SCI1RX|<------------
//          |               |
//          |        CAN1HTX|---> CAN network, ~125kbit/s
//          |        CAN1HRX|<---
//          |          GIOA3|---> CAN transceiver enable
//          |               |
//          +---------------+
//
// Andreas Dannenberg / John Mangino
// Texas Instruments Inc.
// July 29th 2005
// Built with IAR Embedded Workbench Version: 4.30A
//------------------------------------------------------------------------------

#include "stdio.h"
#include "yfuns.h"                              // Customize standard I/O
#include "intrinsic.h"                          // ARM7 specific intrinsics
#include "iotms470r1b1m.h"                      // TMS470 register definitions
#include "tms470r1b1m_bit_definitions.h"

void SCI_Init(void);
void CAN_Init(void);
void HECC1B_irq_handler(void);

void main(void)
{
  PCR = CLKDIV_2;                               // ICLK = SYSCLK / 2
  GCR = ZPLL_CLK_DIV_PRE_1;                     // SYSCLK = 8 x fOSC
  PCR |= PENABLE;                               // Enable peripherals

  HETDCLR = 0xffffffff;                         // Clear HET output latches
  HETDIR = 0xffffffff;                          // Set HET as GIO outputs

  GIODCLRA = 0x08;                              // Clear GIOA3 output latch to
                                                // enable ext. CAN transceiver
  GIODIRA = 0x08;                               // Set GIOA3 to output

  SCI_Init();                                   // Init SCI module
  CAN_Init();                                   // Init High End CAN controller

  REQMASK = (1 << CIM_HECC1B);                  // Enable HECC1B int mask

  printf("\r\n\r\n    *** TMS470 CAN Monitor Demo ***");
  printf("\r\n   ID    RTR DLC D0 D1 D2 D3 D4 D5 D6 D7");

  __enable_interrupt();                         // Enable interrupts

  while (1)                                     // Loop forever...
  {
  }
}
//------------------------------------------------------------------------------
// SCI1 Initialization
//
// Configures the SCI1 UART module for transmit operation using a data
// rate of 115,200bps.
//------------------------------------------------------------------------------
void SCI_Init(void)
{
  SCI1CTL3 &= ~SW_NRESET;                       // Reset SCI1 state machine
  SCI1CCR = TIMING_MODE_ASYNC + CHAR_8;         // Async, 8-bit Char
  SCI1CTL2 |= TXENA;                            // TX enabled
  SCI1CTL3 |= CLOCK;                            // Internal clock
  SCI1LBAUD = 31;                               // 29.4912MHz/8/115,200-1=31
  SCI1PC3 |= TX_FUNC;                           // SCITX is the SCI transmit pin
  SCI1CTL3 |= SW_NRESET;                        // Configure SCI1 state machine
}
//------------------------------------------------------------------------------
// High End CAN controller initialization
//
// Sets up the CAN controller for operation at 125kbit/s. One mailbox is
// initialized for receiving (mailbox 0). Interrupts are enabled to indicate
// incoming messages.
//------------------------------------------------------------------------------
void CAN_Init(void)
{
  // Use CAN1HTX pin for the CAN transmit functions
  HECC1CANTIOC = TXFUNC;

  // Use CAN1HRX pin for the CAN receive functions
  HECC1CANRIOC = RXFUNC;

  // Set HECC1 interrupt configuration. Mailbox 0 (receive mailbox) generates
  // low-priority interrupts (int line 1 --> CIM_HECC1B).
  HECC1CANMIL = MIL0;                              // Use int line 1 for mbox 0
  HECC1CANMIM = MIM0;                              // Enable int for mbox 0
  HECC1CANGIM = I1EN;                              // Enable int line 1

  // Setup master control register
  // Enable configuration mode, activate auto bus on after bus off condition
  HECC1CANMC = CCR + ABO;

  // Wait until CPU has access to CAN configuration registers
  while (!(HECC1CANES & CCE));

  // Setup CAN bit timing for ~125kbit/s
  // 8.07us nominal bit time w/ 17TQs/bit, sample point is located
  // at 7.12us (15TQ)
  // BRP = 13 (Prescaler 14, w/ ICLK = 29.4912MHz)
  // Sample 3x, TSEG1 = 14, TSEG2 = 2, SJW = 1
  HECC1CANBTC = (13 << 16) + SAM + TSEG1_14 + TSEG2_2 + SJW_1;

  // Setup local acceptance mask LAM0
  // Receive any incoming standard/extended ID message
  HECC1CANLAM0 = LAMI + 0x1fffffff;

  // Configure mailbox 0 for receive
  HECC1CANMID0 = AME;                              // Uses acceptance mask LAM0
  HECC1CANMCF0 = 0x00;
  HECC1CANMDL0 = 0x00;
  HECC1CANMDH0 = 0x00;

  HECC1CANMD = MD0;                               // Use mbox 0 for RX
  HECC1CANOPC = OPC0;                             // Protect against overwrite
  HECC1CANME = ME0;                               // Enable mailbox 0

  // Start CAN module
  HECC1CANMC &= ~CCR;

  // Wait until CAN module is started
  while (HECC1CANES & CCE);
}
//------------------------------------------------------------------------------
// SCI1 UART based character output function to be used by __write().
//------------------------------------------------------------------------------
int MyLowLevelPutchar(int x)
{
  while (!(SCI1CTL2 & TXRDY));                  // TX buffer ready?
  SCI1TXBUF = x;                                // Transmit character
  return x;                                     // Indicate "no error"
}
//------------------------------------------------------------------------------
// Provide custom low-level __write() function to be used for console I/O.
// This function is based on the IAR template file <...>\arm\src\lib\write.c
//------------------------------------------------------------------------------
size_t __write(int handle, const unsigned char * buffer, size_t size)
{
  size_t nChars = 0;

  if (buffer == 0)
  {
    /*
     * This means that we should flush internal buffers.  Since we
     * don't we just return.  (Remember, "handle" == -1 means that all
     * handles should be flushed.)
     */
    return 0;
  }

  /* This template only writes to "standard out" and "standard err",
   * for all other file handles it returns failure.
   */
  if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
  {
    return _LLIO_ERROR;
  }

  for (/* Empty */; size != 0; --size)
  {
    if (MyLowLevelPutchar(*buffer++) < 0)
    {
      return _LLIO_ERROR;
    }

    ++nChars;
  }

  return nChars;
}
//------------------------------------------------------------------------------
// HECC1B Interrupt Handler
//
// Checks if a new CAN message was received into mailbox 0, and outputs the
// decoded message using printf().
//------------------------------------------------------------------------------
void HECC1B_irq_handler(void)
{
  if (HECC1CANGIF1 & GMIF1)                        // Msg received?
    if ((HECC1CANGIF1 & 0xf) == MIV1_0)            // Mailbox 0?
    {
      if (HECC1CANMID0 & IDE)                      // Extended identifier?
        printf("\r\n%08x", HECC1CANMID0 & 0x1fffffff);  // Print ext. ID
      else
        printf("\r\n     %03x", (HECC1CANMID0 >> 18) & 0x7ff);  // Print std. ID

      if (HECC1CANMCF0 & RTR)                      // Remote TX request?
        printf(" RTR");                         // Yes
      else
        printf("    ");                         // No

      unsigned int DLC_Temp = HECC1CANMCF0 & 0x7;  // Get DLC field

      printf(" %02x", DLC_Temp);                // Print DLC

      if (DLC_Temp--) { printf("  %02x", HECC1CANMDL0 >> 24);
        if (DLC_Temp--) { printf(" %02x", (HECC1CANMDL0 >> 16) & 0xff);
          if (DLC_Temp--) { printf(" %02x", (HECC1CANMDL0 >>  8) & 0xff);
            if (DLC_Temp--) { printf(" %02x",  HECC1CANMDL0        & 0xff);
              if (DLC_Temp--) { printf(" %02x",  HECC1CANMDH0 >> 24);
                if (DLC_Temp--) { printf(" %02x", (HECC1CANMDH0 >> 16) & 0xff);
                  if (DLC_Temp--) { printf(" %02x", (HECC1CANMDH0 >>  8) & 0xff);
                    if (DLC_Temp)     printf(" %02x",  HECC1CANMDH0        & 0xff);
      }}}}}}}

      HECC1CANRMP = RMP0;                          // Clear flag, new msg can be
    }                                           // received now
}
//------------------------------------------------------------------------------
// TMS470R1B1M Standard Interrupt Handler
//------------------------------------------------------------------------------

__irq __arm void irq_handler(void)
{
  switch ((IRQIVEC & 0xff) - 1)                 // Convert IVEC index to
  {                                             // CIM interrupt channel
    case CIM_HECC1B :                           // HECC1 interrupt B

      HECC1B_irq_handler();
      break;
  }
}