myadder.tan.qmsg

基于ALTERA 公司cyclone系列FPGA的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 23 13:40:26 2007 " "Info: Processing started: Mon Jul 23 13:40:26 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off myadder -c myadder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myadder -c myadder --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] sum\[0\] 12.089 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"sum\[0\]\" is 12.089 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns a\[0\] 1 PIN PIN_240 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 1; PIN Node = 'a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "adder4.v" "" { Text "D:/program/FPGA/adder/adder4.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.449 ns) + CELL(0.590 ns) 7.514 ns myadder:adder0\|Add1~23 2 COMB LC_X1_Y16_N4 1 " "Info: 2: + IC(5.449 ns) + CELL(0.590 ns) = 7.514 ns; Loc. = LC_X1_Y16_N4; Fanout = 1; COMB Node = 'myadder:adder0\|Add1~23'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.039 ns" { a[0] myadder:adder0|Add1~23 } "NODE_NAME" } } { "myadder.v" "" { Text "D:/program/FPGA/adder/myadder.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.467 ns) + CELL(2.108 ns) 12.089 ns sum\[0\] 3 PIN PIN_62 0 " "Info: 3: + IC(2.467 ns) + CELL(2.108 ns) = 12.089 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'sum\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.575 ns" { myadder:adder0|Add1~23 sum[0] } "NODE_NAME" } } { "adder4.v" "" { Text "D:/program/FPGA/adder/adder4.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.173 ns ( 34.52 % ) " "Info: Total cell delay = 4.173 ns ( 34.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.916 ns ( 65.48 % ) " "Info: Total interconnect delay = 7.916 ns ( 65.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.089 ns" { a[0] myadder:adder0|Add1~23 sum[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.089 ns" { a[0] a[0]~out0 myadder:adder0|Add1~23 sum[0] } { 0.000ns 0.000ns 5.449ns 2.467ns } { 0.000ns 1.475ns 0.590ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 23 13:40:27 2007 " "Info: Processing ended: Mon Jul 23 13:40:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}