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📄 cr_sender.mdl

📁 扩频同步时频域二维分布 R=[x,y] surf(R) x:-5:0.1:5 y:-0.01:0.005:0.1
💻 MDL
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	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      DataTypeConversion
      OutDataTypeMode	      "Inherit via back propagation"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      ConvertRealWorld	      "Real World Value (RWV)"
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      FrameConversion
      OutFrame		      "Frame based"
    }
    Block {
      BlockType		      Fcn
      Expr		      "sin(u[1])"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Inport
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Configuration Parameters: Optimiza"
"tion)"
      LogicDataType	      "uint(8)"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Product
      Inputs		      "2"
      Multiplication	      "Element-wise(.*)"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      RateTransition
      Integrity		      on
      Deterministic	      on
      X0		      "0"
      OutPortSampleTime	      "-1"
    }
    Block {
      BlockType		      RealImagToComplex
      Input		      "Real and imag"
      ConstantPart	      "0"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Rounding
      Operator		      "floor"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      Sin
      SineType		      "Time based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Bias		      "0"
      Frequency		      "1"
      Phase		      "0"
      Samples		      "10"
      Offset		      "0"
      SampleTime	      "-1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      ToWorkspace
      VariableName	      "simulink_output"
      MaxDataPoints	      "1000"
      Decimation	      "1"
      SampleTime	      "0"
      FixptAsFi		      off
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "cr_sender"
    Location		    [142, 131, 1118, 663]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Sin
      Name		      "Cos Wave"
      Ports		      [0, 1]
      Position		      [650, 155, 680, 185]
      SineType		      "Time based"
      Frequency		      "500*2*pi"
      Phase		      "pi/2"
      SampleTime	      "0.01/8/4"
    }
    Block {
      BlockType		      Sin
      Name		      "CosL"
      Ports		      [0, 1]
      Position		      [660, 515, 690, 545]
      SineType		      "Time based"
      Frequency		      "3173.0086"
      Phase		      "pi/2"
      SampleTime	      "0.01/8/4"
    }
    Block {
      BlockType		      DataTypeConversion
      Name		      "Data Type Conversion"
      Position		      [330, 243, 405, 277]
      OutDataTypeMode	      "double"
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	off
      SampleTime	      "0.01"
    }
    Block {
      BlockType		      DataTypeConversion
      Name		      "Data Type Conversion1"
      Position		      [340, 603, 415, 637]
      OutDataTypeMode	      "double"
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	off
      SampleTime	      "0.01"
    }
    Block {
      BlockType		      Reference
      Name		      "DelayL"
      Ports		      [1, 1]
      Position		      [895, 565, 950, 605]
      FontSize		      10
      SourceBlock	      "dspsigops/Delay"
      SourceType	      "Delay"
      dly_unit		      "Samples"
      delay		      "480"
      ic_detail		      off
      dif_ic_for_ch	      off
      dif_ic_for_dly	      off
      ic		      "0"
      reset_popup	      "None"
    }
    Block {
      BlockType		      Reference
      Name		      "DelayR"
      Ports		      [1, 1]
      Position		      [890, 205, 945, 245]
      FontSize		      10
      SourceBlock	      "dspsigops/Delay"
      SourceType	      "Delay"
      dly_unit		      "Samples"
      delay		      "320"
      ic_detail		      off
      dif_ic_for_ch	      off
      dif_ic_for_dly	      off
      ic		      "0"
      reset_popup	      "None"
    }
    Block {
      BlockType		      Fcn
      Name		      "Fcn"
      Position		      [435, 245, 495, 275]
      Expr		      "2*u-1"
      SampleTime	      "0.01"
    }
    Block {
      BlockType		      Fcn
      Name		      "Fcn1"
      Position		      [445, 605, 505, 635]
      Expr		      "2*u-1"
      SampleTime	      "0.01"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator"
      Ports		      [2, 1]
      Position		      [255, 242, 285, 273]
      Operator		      "XOR"
      AllPortsSameDT	      off
      OutDataTypeMode	      "Boolean"
      SampleTime	      "0.01"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator1"
      Ports		      [2, 1]
      Position		      [265, 602, 295, 633]
      Operator		      "XOR"
      AllPortsSameDT	      off
      OutDataTypeMode	      "Boolean"
      SampleTime	      "0.01"
    }
    Block {
      BlockType		      Reference
      Name		      "PN Sequence\nGenerator"
      Ports		      [0, 1]
      Position		      [130, 298, 210, 342]
      SourceBlock	      "commseqgen2/PN Sequence\nGenerator"
      SourceType	      "PN Sequence Generator"
      poly		      "[1 0 0 1 0 1]"
      ini_sta		      "[1 1 1 1 1]"
      shift		      "0"
      Ts		      "0.01"
      frameBased	      off
      sampPerFrame	      "1"
      reset		      off
    }
    Block {
      BlockType		      Reference
      Name		      "PN Sequence\nGenerator1"
      Ports		      [0, 1]
      Position		      [140, 658, 220, 702]
      SourceBlock	      "commseqgen2/PN Sequence\nGenerator"
      SourceType	      "PN Sequence Generator"
      poly		      "[1 0 0 1 0 1]"
      ini_sta		      "[1 1 1 1 1]"
      shift		      "0"
      Ts		      "0.01"
      frameBased	      off
      sampPerFrame	      "1"
      reset		      off
    }
    Block {
      BlockType		      Product
      Name		      "Product"
      Ports		      [2, 1]
      Position		      [735, 252, 765, 283]
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
      SampleTime	      "0.01/8/4"
    }
    Block {
      BlockType		      Product
      Name		      "Product1"
      Ports		      [2, 1]
      Position		      [735, 162, 765, 193]
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
      SampleTime	      "0.01/8/4"
    }
    Block {
      BlockType		      Product
      Name		      "Product2"
      Ports		      [2, 1]
      Position		      [745, 612, 775, 643]
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
      SampleTime	      "0.01/8/4"

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