flowlabtc.gfl

it describe how to develop the field programmable gate array

# Verilog : PDCL (jhdparse)
__projnav/pn_correlation_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/pn_correlation_fsm_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/fifo_status_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/fifo_2048x8_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/ch_fifo_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/pn_correlator_jhdparse_tcl.rsp
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : View Verilog Source
MyDCM.v
# Verilog : View Verilog Instantiation Template
automake.err
# Verilog : PDCL (jhdparse)
__projnav/ch_fifo_jhdparse_tcl.rsp
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : View Verilog Source
MyDCM.v
# Verilog : View Verilog Instantiation Template
automake.err
# Verilog : PDCL (jhdparse)
__projnav/ch_fifo_jhdparse_tcl.rsp
# xst flow : RunXST
ch_fifo.syr
ch_fifo.ngr
ch_fifo.prj
ch_fifo.sprj
ch_fifo.ana
ch_fifo.stx
ch_fifo.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/ch_fifo_jhdparse_tcl.rsp
# xst flow : RunXST
ch_fifo.syr
ch_fifo.ngr
ch_fifo.prj
ch_fifo.sprj
ch_fifo.ana
ch_fifo.stx
ch_fifo.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/ch_fifo_jhdparse_tcl.rsp
# xst flow : RunXST
ch_fifo.syr
ch_fifo.ngr
ch_fifo.prj
ch_fifo.sprj
ch_fifo.ana
ch_fifo.stx
ch_fifo.cmd_log
ch_fifo.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
w:\marial\v5\labs\flow\verilog/_ngo
ch_fifo.ngd
ch_fifo_ngdbuild.nav
ch_fifo.bld
.untf
ch_fifo.cmd_log
# Implementation : Map
ch_fifo.nc1
ch_fifo.mrp
ch_fifo.pcf
ch_fifo.ngm
ch_fifo_map.ngm
ch_fifo.mdf
ch_fifo_map.ncd
__projnav/map.log
ch_fifo.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
ch_fifo.twr
ch_fifo.twx
ch_fifo.tsi
ch_fifo.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
ch_fifo.ncd
ch_fifo.par
ch_fifo.pad
ch_fifo.dly
ch_fifo.xpi
ch_fifo.grf
ch_fifo.itr
ch_fifo_last_par.ncd
__projnav/par.log
ch_fifo.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
w:\marial\v5\labs\flow\verilog/_ngo
ch_fifo.ngd
ch_fifo_ngdbuild.nav
ch_fifo.bld
myucf.ucf.untf
ch_fifo.cmd_log
# Implementation : Map
ch_fifo.nc1
ch_fifo.mrp
ch_fifo.pcf
ch_fifo.ngm
ch_fifo_map.ngm
ch_fifo.mdf
ch_fifo_map.ncd
__projnav/map.log
ch_fifo.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
ch_fifo.twr
ch_fifo.twx
ch_fifo.tsi
ch_fifo.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
ch_fifo.ncd
ch_fifo.par
ch_fifo.pad
ch_fifo.dly
ch_fifo.xpi
ch_fifo.grf
ch_fifo.itr
ch_fifo_last_par.ncd
__projnav/par.log
ch_fifo.cmd_log
# Implmentation : Post-Map Static Timing
__projnav/pretrc.log
ch_fifo_preroute.twr
ch_fifo_preroute.twx
ch_fifo.twx_map
ch_fifo.tsi
ch_fifo.tw1
ch_fifo.cmd_log
# Implmentation : Post-Map Static Timing Report