ch_fifo.sprj

it describe how to develop the field programmable gate array

`timescale 1ns/1ns
`include "MyDCM.v"
`include "fifo_2048x8.v"
`include "fifo_status.v"
`include "pn_correlation.v"
`include "pn_correlation_fsm.v"
`include "pn_correlator.v"
`include "ch_fifo.v"
`include "Y:/XILI/QualityPartnerBuild3/verilog/src/iSE/unisim_comp.v"