ch_fifo.twr

it describe how to develop the field programmable gate array

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Release 5.1i - Trace F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Y:/XILI/QualityPartnerBuild3/bin/nt/trce.exe -quiet -e 3 -l 3 -xml ch_fifo
ch_fifo.ncd -o ch_fifo.twr ch_fifo.pcf

Design file:              ch_fifo.ncd
Physical constraint file: ch_fifo.pcf
Device,speed:             xc2v40,-4 (ADVANCED 1.108 2002-06-12, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock wr_clk_in
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
data_ch        |    1.840(R)|   -0.765(R)|
rd             |    4.219(R)|   -3.368(R)|
reset          |    4.975(R)|   -4.432(R)|
---------------+------------+------------+

Clock wr_clk_in to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
almost_empty   |    5.882(R)|
almost_full    |    5.883(R)|
empty          |    5.883(R)|
full           |    5.882(R)|
pn_lock_rd_clk |    7.600(R)|
rd_data<0>     |    9.686(R)|
rd_data<1>     |    9.993(R)|
rd_data<2>     |    9.738(R)|
rd_data<3>     |    9.083(R)|
rd_data<4>     |    9.698(R)|
rd_data<5>     |    9.391(R)|
rd_data<6>     |    9.391(R)|
rd_data<7>     |    9.465(R)|
---------------+------------+

Clock to Setup on destination clock wr_clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_in      |    6.717|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Jul 11 16:52:12 2002
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