mydcm_arwz.ucf

it describe how to develop the field programmable gate array

# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST MyDCM_inst CLK_FEEDBACK = 1X;
INST MyDCM_inst CLKDV_DIVIDE = 2;
INST MyDCM_inst CLKFX_DIVIDE = 1;
INST MyDCM_inst CLKFX_MULTIPLY = 4;
INST MyDCM_inst CLKIN_DIVIDE_BY_2 = FALSE;
INST MyDCM_inst CLKIN_PERIOD = 10;
INST MyDCM_inst CLKOUT_PHASE_SHIFT = NONE;
INST MyDCM_inst DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST MyDCM_inst DFS_FREQUENCY_MODE = LOW;
INST MyDCM_inst DLL_FREQUENCY_MODE = LOW;
INST MyDCM_inst DUTY_CYCLE_CORRECTION = TRUE;
INST MyDCM_inst PHASE_SHIFT = 0;
INST MyDCM_inst STARTUP_WAIT = FALSE;